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KR960035625A - Back bias voltage generation circuit of semiconductor memory device - Google Patents

Back bias voltage generation circuit of semiconductor memory device Download PDF

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Publication number
KR960035625A
KR960035625A KR1019950007521A KR19950007521A KR960035625A KR 960035625 A KR960035625 A KR 960035625A KR 1019950007521 A KR1019950007521 A KR 1019950007521A KR 19950007521 A KR19950007521 A KR 19950007521A KR 960035625 A KR960035625 A KR 960035625A
Authority
KR
South Korea
Prior art keywords
bias voltage
back bias
mode operation
refresh
level
Prior art date
Application number
KR1019950007521A
Other languages
Korean (ko)
Other versions
KR0142953B1 (en
Inventor
유제환
유승문
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950007521A priority Critical patent/KR0142953B1/en
Publication of KR960035625A publication Critical patent/KR960035625A/en
Application granted granted Critical
Publication of KR0142953B1 publication Critical patent/KR0142953B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리 장치의 백바이어스 전압 발생회로에 관한 것이다.The present invention relates to a back bias voltage generating circuit of a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

셀프 리프레쉬 모드에서 소모되는 전류를 감소기키고, 일정 레벨의 백바이어스 전압을 발생하며, 셀프 리프레쉬 모드에서 노말 모드로의 동작을 수행할시 백바이어스 전압레벨을 용이하게 셋업시키는 백바이어스 전압 발생회로를 구현한다.Back bias voltage generation circuit reduces current consumption in self-refresh mode, generates a certain level of back bias voltage, and easily sets up back bias voltage level when performing normal mode in self-refresh mode. Implement

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

리프레쉬 활성화 신호에 응답하여 리프레쉬 모든 동작시 비활성화되고, 노말모드동작시 활성화되어 충전 펌프 클럭을 발생하는 발진수단과; 상기 충전 펌프 클럭에 응답하여 노말모드 동작시 정상레벨의 백바이어스 전압을 발생하고, 리프레쉬 모드 동작시 기준레벨의 백바이어스 전압을 발생하는 충전 펌핑 수단으로 구성한다.An oscillating means which is deactivated during all refresh operations in response to the refresh activation signal, and is activated during normal mode operation to generate a charge pump clock; And a charge pumping means for generating a back bias voltage at a normal level during normal mode operation and a back bias voltage at a reference level during refresh mode operation in response to the charge pump clock.

4. 발명의 중요한 용도셀프 리프레쉬 모드에서 소모되는 전류의 양을 감소시킬 수 있다.4. Significant Uses of the Invention It is possible to reduce the amount of current consumed in the self refresh mode.

Description

반도체 메모리 장치의 백바이어스 전압 발생회로Back bias voltage generation circuit of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 백바이어스 전압 발생회로의 구성도.3 is a configuration diagram of a back bias voltage generation circuit according to the present invention.

Claims (3)

반도체 메모리 장치의 기판에 백바이어스 전압을 공급하는 백바이어스 전압 발생회로에 있어서, 리프레쉬 활성화 신호에 응답하여 리프레쉬모드 동작시 비활성화되고, 노말모드 동작시 활성화되어 충전 펌프 클럭을 발생하는 발진수단과, 상기 충전 펌프 클럭에 응답하여 노말모드 동작시 정상레벨의 백바이어스 전압을 발생하고, 상기 리프레쉬 모드 동작시 기준레벨의 백바이어스 전압을 발생하는 충전 펌핑 수단으로 구성됨을 특징으로 하는 백바이어스 전압 발생회로.A back bias voltage generation circuit for supplying a back bias voltage to a substrate of a semiconductor memory device, the back bias voltage generating circuit comprising: an oscillating means which is inactivated during a refresh mode operation in response to a refresh activation signal and is activated during a normal mode operation to generate a charge pump clock; And a charge pumping means for generating a back bias voltage at a normal level during normal mode operation in response to a charge pump clock, and for generating a back bias voltage at a reference level during the refresh mode operation. 제1항에 있어서, 상기 충전 펌핑 수단은, 상기 노말모드 동작시 상기 정상레벨의 백바이어스 전압을 발생하고, 상기 리프레쉬 모드 동작시 상기 정상레벨의 백바이어스 전압의 절대값보다 작은 레벨의 상기 기준레벨의 백바이어스 전압을 발생하는 것을 특징으로 하는 백바이어스 전압 발생회로.The reference level of claim 1, wherein the charge pumping means generates the back bias voltage of the normal level in the normal mode operation, and the reference level at a level smaller than an absolute value of the back bias voltage of the normal level in the refresh mode operation. A back bias voltage generation circuit, characterized in that for generating a back bias voltage. 제1항에 있어서, 상기 충전 펌핑 수단은, 접지전압의 상기 기준레벨의 백바이어스 전압을 발생하는 것을 특징으로 하는 백바이어스 전압 발생회로.The back bias voltage generating circuit according to claim 1, wherein said charge pumping means generates a back bias voltage of said reference level of ground voltage. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007521A 1995-03-31 1995-03-31 Back bias voltage generation circuit of semiconductor memory device KR0142953B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007521A KR0142953B1 (en) 1995-03-31 1995-03-31 Back bias voltage generation circuit of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007521A KR0142953B1 (en) 1995-03-31 1995-03-31 Back bias voltage generation circuit of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR960035625A true KR960035625A (en) 1996-10-24
KR0142953B1 KR0142953B1 (en) 1998-08-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007521A KR0142953B1 (en) 1995-03-31 1995-03-31 Back bias voltage generation circuit of semiconductor memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327626B2 (en) 2005-08-17 2008-02-05 Hynix Semiconductor Inc. Self refresh control device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100833587B1 (en) * 2001-12-22 2008-05-30 주식회사 하이닉스반도체 Semiconductor memory device for improving refresh characteristics
KR100649973B1 (en) 2005-09-14 2006-11-27 주식회사 하이닉스반도체 Internal voltage generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7327626B2 (en) 2005-08-17 2008-02-05 Hynix Semiconductor Inc. Self refresh control device
US7580310B2 (en) 2005-08-17 2009-08-25 Hynix Semiconductor, Inc. Self refresh control device

Also Published As

Publication number Publication date
KR0142953B1 (en) 1998-08-17

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