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KR960032282A - Output circuit for driving the liquid crystal display - Google Patents

Output circuit for driving the liquid crystal display Download PDF

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Publication number
KR960032282A
KR960032282A KR1019950003706A KR19950003706A KR960032282A KR 960032282 A KR960032282 A KR 960032282A KR 1019950003706 A KR1019950003706 A KR 1019950003706A KR 19950003706 A KR19950003706 A KR 19950003706A KR 960032282 A KR960032282 A KR 960032282A
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KR
South Korea
Prior art keywords
signal
output
transistor
circuit
drain
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KR1019950003706A
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Korean (ko)
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KR100188081B1 (en
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김천호
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김광호
삼성전자 주식회사
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Publication of KR960032282A publication Critical patent/KR960032282A/en
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Publication of KR100188081B1 publication Critical patent/KR100188081B1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

이 발명은 액정 표시 장치를 구동하기 위한 출력 회로에 관한 것으로, 종래의 출력 구동 회로가 많은 트랜지스터로 구성되어 있기 때문에 회로내에 출력단자수가 많아지는 경우 많은 면적을 차지해서 집적회로 구성에 부담이 되기 때문에, 이러한 단점을 해결하기 위해서 종래 회로와 동일한 기능을 보유하면서도 사용된 트랜지스터를 줄임으로 집적 회로를 소형화, 박형화하고자 하는 액정 표시 장치를 구동하기 위한 출력 회로에 관한 것이다.The present invention relates to an output circuit for driving a liquid crystal display device. Since the conventional output drive circuit is composed of many transistors, when the number of output terminals in the circuit increases, it occupies a large area and burdens the integrated circuit configuration. In order to solve this disadvantage, the present invention relates to an output circuit for driving a liquid crystal display device which is intended to reduce the size and thickness of an integrated circuit by reducing transistors used while maintaining the same function as a conventional circuit.

Description

액정 표시 장치를 구동하기 위한 출력 회로Output circuit for driving the liquid crystal display

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 액정 표시 장치를 구동하기 위한 출력 회로의 상세 회로도이다.2 is a detailed circuit diagram of an output circuit for driving a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (6)

데이타 신호 입력과 출력 신호의 교류화 신호 입력의 두 신호를 받아 각 신호에서 서로 반전된 두가지 상태의 신호를 발생시켜 출력하는 인버터 회로부(40), 인버터 회로부(40)에서 발생된 신호를 조합하여 출력 회로부에 있는 출력전압 제어용 트랜지스터의 게이트 제어 신호를 발생시켜 출력하는 조합 회로부(50)와, 조합 회로부(50)에서 발생된 게이트 제어 신호를 받아 그 신호로 인해 도통된 출력 전압 제어용 트랜지스터를 통해 액정 표시 장치 구동용 전압을 출력하는 구동 회로부(60)로 구성되어 있는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.Inverter circuit section 40, which receives two signals of data signal input and output signal alternating signal input, generates and outputs two signals which are inverted from each other, and outputs a combination of signals generated from inverter circuit section 40 and inverter circuit section 40. The combination circuit unit 50 which generates and outputs the gate control signal of the output voltage control transistor in the circuit unit and the gate voltage control signal generated by the combination circuit unit 50 and receives the gate voltage control signal and is conducted through the transistor. An output circuit for driving a liquid crystal display device, characterized by comprising a drive circuit section 60 for outputting a device driving voltage. 제1항에 있어서, 상기한 인버터 회로부(40)는 신호를 반전시키는 4개의 인버터 회로(IN1,IN2,IN3,IN4)가 데이타 신호(D)과 출력 신호의 교류화 신호선(M)에 각각 2개씩 직렬로 연결되어 있으며 각 신호선의 2개의 인버터 회로에서 첫번째 인버터 회로(D의 IN1,M의 IN3)에서는 반전(역위상)신호 출력(ⓐ,ⓑ)을, 두번째 인버터 회로(D의 IN2, M의 IN4)에서는 비반전(동위상) 신호 출력(ⓐ,ⓑ)을 발생시킬 수 있도록 이루어지는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.4. The inverter circuit unit 40 according to claim 1, wherein four inverter circuits IN1, IN2, IN3, and IN4 for inverting the signal are respectively provided to the alternating signal line M of the data signal D and the output signal. The two inverter circuits of each signal line are connected in series, and the inverting (antiphase) signal outputs (ⓐ, ⓑ) are connected to the first inverter circuit (IN1 of IN D and IN3 of M), and the second inverter circuits (IN2, M of D). IN4), an output circuit for driving a liquid crystal display device, characterized in that it is possible to generate a non-inverting (in-phase) signal output (ⓐ, ⓑ). 제1항에 있어서, 상기한 조합 회로부(50)는 데이타 신호선(D)의 동위상 신호(ⓑ)가 피모스형 트랜지스터 (PMOS1)와 엔모스형 트랜지스터(NMOS1)의 게이트에 연결되고, 피모스형 트랜지스터(PMOS1)의 소오스에는 VDD, 드레인에는 피모스형 트랜지스터(PMOS2), 엔모스형 트랜지스터(NMOS2)의 드레인(혹은 소오스)에 연결되어 출력하고, (ⓔ), 엔모스형 트랜지스터(NMOS1)의 소오스에는 VEE, 드렝니에는 피모스형 트랜지스터(PMOS2), 엔모스형 트랜지스터(NMOS2)의 소오스(혹은 드레인)에 연결되어 출력하고(ⓕ), 데이타 신호(D)의 역위상 신호(ⓐ)가 피모스형 트랜지스터(PMOS4)와 엔모스형 트랜지스터(NMOS4)의 게이트에 연결되고, 피모스형 트랜지스터(PMOS4)의 소오스에는 VDD, 드레인에는 피모스형 트랜지스터(PMOS5), 엔모스형 트랜지스터(NMOS5)의 드레인 (혹은 소오스)에 연결되어 출력하고(ⓖ), 엔모스형 트랜지스터(NMOS4)의 소오스에는 VEE, 드레인에는 피모스형 트랜지스터(PMOS5), 엔모스형 트랜지스터(NMOS5)의 소오스(혹은 드레인)에 연결되어 출력하고(ⓗ), 출력신호의 교류화 신호(M)의 역위상 신호(ⓒ)가 피모스형 트랜지스터(PMOS2)와 엔모스형 트랜지스터(NMOS5)의 게이트에, 출력신호의 교류화 신호(M)의 동위상 신호(ⓓ)가 엔모스형 트랜지스터(NMOS2)와 피모스형 트랜지스터(PMOS5) 게이트에 인가되는 형태로 이루어지는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.2. The combination circuit unit 50 of claim 1, wherein the in-phase signal ⓑ of the data signal line D is connected to the gates of the PMOS transistor PMOS1 and the NMOS transistor NMOS1, The source of the transistor PMOS1 is connected to the output of VDD, the drain of the PMOS transistor PMOS2, and the drain of the NMOS transistor NMOS2 (or source). Is connected to the source (or drain) of the PMOS transistor (PMOS2) and the NMOS transistor (NMOS2) at the source of VEE, and the output signal is generated from the antiphase signal (ⓐ) of the data signal (D). Is connected to the gates of the PMOS transistor PMOS4 and the NMOS transistor NMOS4, the source of the PMOS transistor PMOS4 is VDD, the drain is the PMOS transistor PMOS5, and the NMOS transistor NMOS5. ) Connected to the drain (or source) (Ⓖ), connected to the source (or drain) of the NMOS transistor NMOS4, VEE for the source, PMOS transistor PMOS5 for the drain, and NMOS5 transistor (NMOS5) for output, and output The in-phase signal ⓒ of the alternating signal M of the signal is the in-phase signal ⓓ of the alternating signal M of the output signal to the gates of the PMOS transistor PMOS2 and the NMOS transistor NMOS5. ) Is applied to an NMOS transistor (NMOS2) and a PMOS transistor (PMOS5) gate, the output circuit for driving a liquid crystal display device. 제1항에 있어서, 상기한 구동 회로부(60)는 상기한 조합 회로부(50)의 피모스형 트랜지스터(PMOS1)의 드레인 출력(ⓔ)이 피모스형 트랜지스터(PMOS3)의 게이트에 연결되고, 피모스형 트랜지스터(PMOS3)의 소오스에는 VO, 드레인은 출력에 연결되고, 상기한 조합 회로부(50)의 엔모스형 트랜지스터(NMOS1)의 드레인 출력(ⓕ)이 엔모스형 트랜지스터(NMOS3)의 게이트가 연결되며, 엔모스형 트랜지스터(NMOS3)의 소오스는 V4, 드레인은 출력에 연결되고, 상기한 조합 회로부(50)의 피모스형 트랜지스터(PMOS4)의 드레인 출력(ⓖ)이 피모스형 트랜지스터(PMOS6)의 게이트가 연결되고, 피모스형 트랜지스터(PMOS6)의 소오스에는 V1, 드레인은 출력에 연결되고, 상기한 조합 회로부(50)의 엔모스형 트랜지스터(NMOS6)의 소오스에는 V5, 드레인에는 출력이 연결되는 형태로 이루어지는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.2. The driving circuit unit 60 of claim 1, wherein the drain output ⓔ of the PMOS transistor PMOS1 of the combination circuit unit 50 is connected to the gate of the PMOS transistor PMOS3. The source of the MOS transistor PMOS3 is connected to VO and a drain thereof, and the drain output ⓕ of the NMOS transistor NMOS1 of the combination circuit unit 50 is the gate of the NMOS transistor NMOS3. The source of the NMOS transistor NMOS3 is connected to V4 and the drain is connected to the output. The drain output of the PMOS transistor PMOS4 of the combination circuit unit 50 is connected to the PMOS transistor PMOS6. ) Is connected, the source of the PMOS transistor PMOS6 is connected to V1, the drain is connected to the output, and the source of the NMOS transistor NMOS6 of the combined circuit section 50 is connected to the output of V5, and the drain is output. To be connected An output circuit for driving the liquid crystal display device as ranging. 제2항에 있어서, 상기한 반전, 비반전 신호 출력을 발생시키는 회로는 데이타 신호(D)와 출력 신호의 교류와 신호(M)를 서로 바꾸어서도 사용할 수 있도록 구성되는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.The liquid crystal display device according to claim 2, wherein the circuit which generates the inverted and non-inverted signal output is configured to be used even when the data signal D and the alternating current of the output signal and the signal M are interchanged. Output circuit for driving the. 제3항에 있어서, 상기한 출력 신호의 교류와 신호(M)의 역위상 신호(ⓒ)가 피모스형 트랜지스터(PMOS2)와 엔모스형 트랜지스터(NMOS5)의 게이트에, 출력 신호의 교류화 신호(M)의 동위상 신호(ⓓ)가 엔모스형 트랜지스터(NMOS2)와 피모스형 트랜지스터(PMOS5) 게이트에 인가되는 형태의 회로는 출력 신호의 교류화 신호(M)에 따라 동위상 신호(ⓓ)가 인가된 트랜지스터와 역위상 신호(ⓒ)가 인가된 트랜지스터의 도통을 제어해 주는 역할을 하는 회로로써, 그 구성형태를 대신하여 상기한 회로와 동일한 기능을 갖는 회로로 이루어지는 것을 특징으로 하는 액정 표시 장치를 구동하기 위한 출력 회로.4. The alternating signal of the output signal according to claim 3, wherein the alternating current of the output signal and the antiphase signal ⓒ of the signal M are connected to the gates of the PMOS transistor PMOS2 and the NMOS transistor NMOS5. A circuit in which the in-phase signal (ⓓ) of (M) is applied to the gates of the NMOS transistors (NMOS2) and the PMOS transistor (PMOS5) has an in-phase signal (ⓓ) in accordance with the alternating signal (M) of the output signal. Is a circuit which controls the conduction of the transistor to which the transistor) is applied and the transistor to which the anti-phase signal (©) is applied, and has a circuit having the same function as the circuit described above in place of the configuration thereof. Output circuit for driving the display device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950003706A 1995-02-24 1995-02-24 Output circuit for driving the liquid crystal display KR100188081B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950003706A KR100188081B1 (en) 1995-02-24 1995-02-24 Output circuit for driving the liquid crystal display

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Application Number Priority Date Filing Date Title
KR1019950003706A KR100188081B1 (en) 1995-02-24 1995-02-24 Output circuit for driving the liquid crystal display

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KR960032282A true KR960032282A (en) 1996-09-17
KR100188081B1 KR100188081B1 (en) 1999-06-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100628435B1 (en) * 1998-09-15 2006-12-04 삼성전자주식회사 Assembly method of tiled liquid crystal display and tiled liquid crystal display

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4803711B2 (en) 2005-08-25 2011-10-26 オンセミコンダクター・トレーディング・リミテッド Drive circuit for STN-LCD panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100628435B1 (en) * 1998-09-15 2006-12-04 삼성전자주식회사 Assembly method of tiled liquid crystal display and tiled liquid crystal display

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