KR960026643A - 반도체장치의 배선 제조방법 - Google Patents
반도체장치의 배선 제조방법 Download PDFInfo
- Publication number
- KR960026643A KR960026643A KR1019950050135A KR19950050135A KR960026643A KR 960026643 A KR960026643 A KR 960026643A KR 1019950050135 A KR1019950050135 A KR 1019950050135A KR 19950050135 A KR19950050135 A KR 19950050135A KR 960026643 A KR960026643 A KR 960026643A
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- South Korea
- Prior art keywords
- metal wiring
- wiring material
- material layer
- forming
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (9)
- 금속배선재료를 이용하여 물리적 기상 성장법에 의해, 기판상에 금속배선재료층을 형성하는 공정과, 금속배선재료층상에 산화방지막을 형성하는 공정과, 금속배선재료층을 리플로처리하여서 산화방지막을 구성하는 구성성분과 금속배선재료층의 성분과의 완전한 고용체를 형성하는 공정과, 금속배선재료층을 패터닝하여 배선을 형성하는 공정과를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제1항에 있어서, 금속배선재료층상에 산화보호막을 형성하는 공정과 금속배선재료층을 리플로처리하는 공정과의 사이에 반도체장치를 대기에 노출시키는 공정을 더 포함하여 이루어진 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 금속배선재료층으로 이루어진 배선 및 금속배선재료층을 구성하는 금속배선재료로 채워진 접속구멍과를 제공하는 반도체장치의 배선 제조방법에 있어서, 그 상측에 전도층이 제공된 기판상에 절연층을 형성하고, 전도층상에 제공된 절연층내에 개구부를 형성하는 공정과, 물리적 기상 성장법으로 절연층상에 금속배선재료층을 형성하는 공정과, 금속배선재료층상에 산화방지막을 형성하는 공정과, 금속배선재료층을 리플로처리하여서 산화방지막을 구성하는 구성성분과 금속배선재료층의 성분과의 완전한 고용체를 형성하며, 금속배선재료로 개구부를 채워서 접속구멍을 형성하는 공정과, 금속배선재료층을 패터닝하여서 배선을 형성하는 공정과를 포함하는 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제3항에 있어서, 물리적 기상성장법에 의해 절연층상에 금속배선재료층을 형성하는 공정이 실행되어서 개구부가 그 바닥부에 보이드를 보유하며 그 상측부에 금속배선재료층으로 덮혀지게 되며, 금속배선재료층을 리플로처리하는 공정은 고압하에서 실행되는 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 금속배선재료층으로 이루어지는 배선과 금속배선재료층을 구성하는 금속배선재료로 채워지는 접속구멍과를 제공하는 반도체장치의 배선 제조방법에 있어서, 그 위에 전도층이 제공된 기판상에 절연층을 형성하며, 전도층상에 형성된 절연층내에 홈을 형성하는 공정과, 물리적 기상 성장법으로 절연층상에 금속배선재료층을 형성하는 공정과, 금속배선재료층상에 산화방지막을 형성하는 공정과, 금속배선재료층을 리플로처리하여서 산화방지막을 구성하는 구성성분과 금속배선재료층의 성분과의 완전한 고용체를 형성하며, 금속배선재료로 홈을 채워서 접속구멍을 형성하는 공정과, 절연막의 표면으로부터 금속배선재료층을 제거하고, 홈 내부가 채워진 배선을 형성하는 공정과를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제3항 또는 제5항에 있어서, 금속배선재료층상에 산화방지막을 형성하는 공정과 금속배선재료층을 리플로처리하는 공정과의 사이에 반도체장치를 대기에 노출시키는 공정을 더 포함하여 이루어진 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제1항이나 제3항 혹은 제5항에 있어서, 산화방지막은 실온에서 쉽게 견고한 산화막을 형성할 수 없는 재료로 이루어지며, 금속배선재료층을 리플로처리하여서 금속배선재료에 완전히 용해되어서 고용체를 형성하는 한계량 이하의 산화방지막을 구성하는 구성성분의 양을 포함하는 두께에 상당하는 막두께로 이루어지는 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제7항에 있어서, 산화방지막은 은, 구리, 실리콘 및 게르마늄의 일군에서 선택된 적어도 하나의 재료로 이루어지는 것을 특징으로 하는 반도체장치의 배선 제조방법.
- 제1항 또는 제3항에 있어서, 금속배선재료는 Al-Cu합금, Al-Si합금, Al-Si-Cu합금, Al-Ge합금 및 Al-Si-Ge합금인 Al합금의 여러 유형중 하나와 순수한 알루미늄과 순수한 구리 중 하나인 것을 특징으로 하는 반도체장치의 배선 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33424294A JP3365112B2 (ja) | 1994-12-16 | 1994-12-16 | 半導体装置の配線形成方法 |
JP94-334242 | 1994-12-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960026643A true KR960026643A (ko) | 1996-07-22 |
Family
ID=18275140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950050135A Ceased KR960026643A (ko) | 1994-12-16 | 1995-12-14 | 반도체장치의 배선 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5985751A (ko) |
JP (1) | JP3365112B2 (ko) |
KR (1) | KR960026643A (ko) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789317A (en) * | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
US6171957B1 (en) | 1997-07-16 | 2001-01-09 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of semiconductor device having high pressure reflow process |
JP3201321B2 (ja) * | 1997-11-10 | 2001-08-20 | 日本電気株式会社 | 配線用アルミニウム膜の形成方法 |
US6140236A (en) * | 1998-04-21 | 2000-10-31 | Kabushiki Kaisha Toshiba | High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring |
US6982226B1 (en) * | 1998-06-05 | 2006-01-03 | Agere Systems Inc. | Method of fabricating a contact with a post contact plug anneal |
JP2000133712A (ja) * | 1998-08-18 | 2000-05-12 | Seiko Epson Corp | 半導体装置の製造方法 |
KR100309811B1 (ko) * | 1998-12-30 | 2002-07-06 | 박종섭 | 반도체소자의금속배선형성방법 |
TW412792B (en) * | 1999-02-10 | 2000-11-21 | Applied Materials Inc | Etching back process for solving the plug loss |
US6211085B1 (en) * | 1999-02-18 | 2001-04-03 | Taiwan Semiconductor Company | Method of preparing CU interconnect lines |
US6451698B1 (en) * | 1999-04-07 | 2002-09-17 | Koninklijke Philips Electronics N.V. | System and method for preventing electrochemical erosion by depositing a protective film |
JP3892621B2 (ja) * | 1999-04-19 | 2007-03-14 | 株式会社神戸製鋼所 | 配線膜の形成方法 |
US6683761B2 (en) | 2000-11-09 | 2004-01-27 | Seagate Technology Llc | Magnetoresistive sensor with laminate electrical interconnect |
US6436814B1 (en) | 2000-11-21 | 2002-08-20 | International Business Machines Corporation | Interconnection structure and method for fabricating same |
KR100400035B1 (ko) * | 2001-02-21 | 2003-09-29 | 삼성전자주식회사 | 균일한 접촉 저항을 갖는 콘택을 구비한 반도체 소자 및그의 제조방법 |
JP2003023070A (ja) * | 2001-07-05 | 2003-01-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
KR100641502B1 (ko) * | 2002-12-30 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조시 듀얼 다마신 공정을 이용한 콘텍형성방법 |
JP4528510B2 (ja) * | 2003-09-22 | 2010-08-18 | 株式会社東芝 | 半導体レーザ素子用サブマウント |
KR100792358B1 (ko) * | 2006-09-29 | 2008-01-09 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 및 그 형성방법 |
KR101476120B1 (ko) * | 2008-06-12 | 2014-12-26 | 주성엔지니어링(주) | 박막형 태양전지 및 그 제조방법 |
US8487386B2 (en) * | 2009-06-18 | 2013-07-16 | Imec | Method for forming MEMS devices having low contact resistance and devices obtained thereof |
US9960078B1 (en) | 2017-03-23 | 2018-05-01 | International Business Machines Corporation | Reflow interconnect using Ru |
US20230343697A1 (en) * | 2022-04-20 | 2023-10-26 | Samsung Electronics Co., Ltd. | Semiconductor device including spacer via structure and method of manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747361A (en) * | 1991-05-01 | 1998-05-05 | Mitel Corporation | Stabilization of the interface between aluminum and titanium nitride |
KR100281887B1 (ko) * | 1994-01-18 | 2001-03-02 | 윤종용 | 반도체장치의 제조방법 |
US5610099A (en) * | 1994-06-28 | 1997-03-11 | Ramtron International Corporation | Process for fabricating transistors using composite nitride structure |
-
1994
- 1994-12-16 JP JP33424294A patent/JP3365112B2/ja not_active Expired - Fee Related
-
1995
- 1995-12-07 US US08/568,667 patent/US5985751A/en not_active Expired - Fee Related
- 1995-12-14 KR KR1019950050135A patent/KR960026643A/ko not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
JPH08172131A (ja) | 1996-07-02 |
JP3365112B2 (ja) | 2003-01-08 |
US5985751A (en) | 1999-11-16 |
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