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KR960019670A - 반도체칩 패키지 및 그의 제조 방법 - Google Patents

반도체칩 패키지 및 그의 제조 방법 Download PDF

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Publication number
KR960019670A
KR960019670A KR1019950040204A KR19950040204A KR960019670A KR 960019670 A KR960019670 A KR 960019670A KR 1019950040204 A KR1019950040204 A KR 1019950040204A KR 19950040204 A KR19950040204 A KR 19950040204A KR 960019670 A KR960019670 A KR 960019670A
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South Korea
Prior art keywords
thermally conductive
semiconductor chip
substrate
layer
electrically
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KR1019950040204A
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English (en)
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KR100217528B1 (ko
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와렌 윌슨 제임스
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윌리엄 티. 엘리스
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR960019670A publication Critical patent/KR960019670A/ko
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Publication of KR100217528B1 publication Critical patent/KR100217528B1/ko

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Abstract

본 발명은 반도체칩 패키지 및 이를 제조하는 방법에 관한 것으로, 패키지는 마주보는 면상의 열적 및 전기적 도전성 물질(예를 들면, 구리)을 가지는 세라믹 기판을 구비하고, 이들 층은 세라믹내에 제공되는 구멍내에 위치되는 금속 물질에 의해 열적 및 전기적으로 접속된다. 반도체 칩은 이들 층중의 하나상에 장착되고, 일정한 간격을 둔 회로에 전기 접속되는 접속 영역은 바람직한 실시예에서 두 열적 도전층과 동시에 형성된다. 외부 기판(예를 들면, 인쇄배선보드)에 회로를 접속시키는 것은 바람직하게 금속화 스프링 클립을 사용하여 성취된다. 이들 클립은 바람직하게 일정 위치에 납땜된다. 구멍내에 위치되는 바람직한 금속은 땜납이며, 하나의 예는 10 : 90 주석 : 납 땜납이다. 본 발명에서 생산되는 패키지는 칩 및 회로를 보호하기 위하여 상부에 사실상 위치되는 두 분량의 보호 인캡슐런트 물질을 더 포함할 수 있다. 희로에 클립을 접속시키기 위한 바람직한 수단은 와이어 본딩 동작을 사용하는 것이다.

Description

반도체칩 패키지 및 그의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1∼8도는 본 발명의 일 실시예에 따르는 반도체칩 패키지를 생산하는 각종 단계를 도시한 도면으로서, 제8도는 하부 기판(예를 들면, 인쇄배선보드)상에 완성되어 장착되어진 본 발명을 부분적으로 도시한 도면.

Claims (27)

  1. 제1 및 제2 마주보는 면과, 상기 제1 및 제2 마주보는 면을 상호접속시키기 위하여 상기 기판을 연장되는 적어도 하나의 구멍을 포함하는 세라믹 기판과; 상기 기판의 상기 제1면상에 위치되는 제1열적 도전층과; 상기 기판의 상기 제2면상에 위치되는 제2열적 도전층과; 열적 접속 방식으로 상기 제1열적 도전층상에 위치되는 반도체칩과; 상기 제1열적 도전층으로부터 사전결정된 거리에 상기 기판의 상기 제1면상에 위치되고, 상기 제1열적 도전층으로부터 전기적으로 절연되는 회로층으로서, 상기 반도체 칩은 상기 회로층에 전기 접속되는 상기 회로층과; 상기 제1 및 제2열적 도전층을 열적으로 접속시키기 위하여 상기 기판의 상기 구멍내에 위치되는 적어도 하나의 열적 도전성 부재로서, 패키지 동작동안 상기 반도체 칩에 의해 발생되는 열은 상기 제1열적 도전층으로부터 상기 열적 도전성 부재를 통하여 상기 제2열적 도전층으로 전달되는 상기 적어도 하나의 열적 도전성 부재와; 외부 회로화된 기판상의 회로에 상기 회로층을 전기 접속시키는 수단을 포함하는 반도체칩 패키지.
  2. 제1항에 있어서, 상기 제1 및 제2열적 도전층은 금속으로 구성되는 반도체칩 패키지.
  3. 제2항에 있어서, 상기 금속은 구리를 포함하는 반도체칩 패키지.
  4. 제1항에 있어서, 상기 제1열적 도전층 대 상기 제2열적 도전층의 두께의 비는 약 1 : 1 내지 약 1 : 10의 범위내에 있는 반도체칩 패키지.
  5. 제1항에 있어서, 상기 제I열적 도전층에 상기 반도체 칩을 고정시키는 열적 도전성 접착제를 더 포함하는 반도체칩 패키지.
  6. 제1항에 있어서, 상기 접착제는 전기적으로 도전성인 반도체칩 패키지.
  7. 제6항에 있어서, 상기 제1 및 제2열적 도전층과 상기 열적 도전성 부재는 전기적으로 도전성이며, 상기 제2열적 도전층은 상기 패키지에 대하여 접지면으로서 기능하는 반도체칩 패키지.
  8. 제1항에 있어서, 상기 제1 및 제2열적 도전층과 상기 열적 도전성 부재는 전기적으로 도전성이며, 상기 제2열적 도전층은 상기 패키지에 대한 접지면으로서 기능하는 반도체칩 패키지.
  9. 제8항에 있어서, 상기 제2열적 도전층은 상기 기판의 상기 제1면상에 위치되는 상기 회로층에 전기 접속되는 반도체칩 패키지.
  10. 제9항에 있어서, 상기 외부 기판에 상기 회로층을 전기 접속시키는 상기 수단은 상기 회로층에 상기 제2열적 도전층을 전기 접속시키는 반도체칩 패키지.
  11. 제9항에 있어서, 상기 전기적 접속 수단은 전기적 도전성 클립 부재를 구비하는 반도체칩 패키지.
  12. 제1항에 있어서, 상기 전기적 접속 수단은 전기적 도전성 클럽 부재를 구비하는 반도체칩 패키지.
  13. 제1항에 있어서, 적어도 하나의 전기적 도전성 와이어를 더 포함하고, 상기 와이어는 상기 기판상의 상기 회로층에 상기 클립을 전기 접속시키는 반도체칩 패키지.
  14. 제1항에 있어서, 상기 외부 기판은 인쇄배선보드를 구비하는 반도체칩 패키지.
  15. 제1항에 있어서, 상기 세라믹 기판의 상기 구멍내에 위치되는 상기 열적 도전성 부재는 땜납 및 구리로 구성되는 그룹으로부터 선택되는 반도체칩 패키지.
  16. 제15항에 있어서, 상기 열적 도전성 부재는 스터드 부재를 구비하는 반도체칩 패키지.
  17. 제1 및 제2마주보는 면을 가지는 세라믹 기판을 제공하는 단계와; 상기 제1 및 제2마주보는 면을 상호접속시키기 위하여 상기 기판에 적어도 하나의 구멍을 제공하는 단계와; 상기 구멍내에 열적 도전성 부재를 제공하는 단계와; 상기 제1 및 제2마주보는 면상에 각각 제1 및 제2열적 도전층을 제공하고, 상기 구멍내의 열적 도전성 부재는 상기 제1 및 제2열적 도전층을 열적으로 접속시키는 단계와; 상기 제1열적 도전층상에 반도체칩을 위치시켜, 패키지 동작동안 상기 칩이 발생하는 열이 상기 제1열적 도전층으로부터 상기 열적 도전성 부재를 통하여 상기 제2열적 도전층으로 전달되는 단계와; 상기 제1열적 도전층으로부터 일정한 간격을 두고 전기적으로 절연된 위치에 상기 기판의 상기 제1표면상에 회로층을 제공하는 단계와; 상기 회로층에 상기 반도체칩을 전기 접속시키는 단계와; 상기 회로층을 외부 회로화된 기판상의 회로에 전기 접속시키는 수단을 제공하는 단계를 포함하는 반도체칩 패키지를 제조하는 방법.
  18. 제17항에 있어서, 상기 구멍은 드릴링(drilling)에 의해 상기 세라믹 기판에 제공되는 반도체칩 패키지를 제조하는 방법.
  19. 제17항에 있어서, 상기 제1 및 제2열적 도전층은 스퍼터링(sputtering)동작을 사용하여 제공되는 반도체칩 패키지를 제조하는 방법.
  20. 제19항에 있어서, 상기 제1 및 제2열적 도전층은 동시에 제공되는 반도체칩 패키지를 제조하는 방법.
  21. 제20항에 있어서, 상기 회로층은 상기 기판상의 상기 제1 및 제2열적 도전층의 제공과 사실상 동시에 도포되는 반도체칩 패키지를 제조하는 방법.
  22. 제17항에 있어서, 상기 회로층은 포토리소그래틱(photolithography) 동작을 사용하여 도포되는 반도체칩 패키지를 제조하는 방법.
  23. 제22항에 있어서, 상기 포토리소그래피 동작은 상기 제1표면상에 전기적 도전층을 도포하는 단계와, 상기 전기적 도전층상에 포토레지스트(photoresist)를 도포, 노출 및 현상시키는 단계들 및 상기 도전층의 선택된 부분을 에칭하는 단계를 포함하는 반도체칩 패키지를 제조하는 방법.
  24. 제23항에 있어서, 상기 포토리소그래피 동작 단계는 상기 회로층의 도포와 사실상 동시에 상기 제1 및 제2열적 도전층을 제공하기 위하여 더 사용되는 반도체칩 패키지를 제조하는 방법.
  25. 제17항에 있어서, 상기 칩은 와이어본딩 동작을 사용하여 상기 회로층에 전기 접속되는 반도체칩 패키지를 제조하는 방법.
  26. 제17항에 있어서, 상기 열적 도전성 부재는 납땜 동작을 사용하여 상기 세라믹의 상기 구멍내에 제공되는 반도체칩 패키지를 제조하는 방법.
  27. 제17항에 있어서, 상기 반도체칩 위에 보호 인캡슐런트(protective encapsulant)를 도포하는 단계를 더 포함하는 반도체칩 패키지를 제조하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950040204A 1994-11-09 1995-11-08 반도체 칩 패키지 및 그의 제조 방법 KR100217528B1 (ko)

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CN1093689C (zh) 2002-10-30
US5561322A (en) 1996-10-01
KR100217528B1 (ko) 1999-09-01
JPH08213510A (ja) 1996-08-20
SG54966A1 (en) 1998-12-21
MY115175A (en) 2003-04-30
CN1155163A (zh) 1997-07-23

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