KR960005180Y1 - Automatic Balance Level Control Circuit - Google Patents
Automatic Balance Level Control Circuit Download PDFInfo
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- KR960005180Y1 KR960005180Y1 KR2019910004530U KR910004530U KR960005180Y1 KR 960005180 Y1 KR960005180 Y1 KR 960005180Y1 KR 2019910004530 U KR2019910004530 U KR 2019910004530U KR 910004530 U KR910004530 U KR 910004530U KR 960005180 Y1 KR960005180 Y1 KR 960005180Y1
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- transistor
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- resistor
- level control
- automatic balance
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- 230000007257 malfunction Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
내용없음.None.
Description
제1도는 종래 자동 발란스 레벨 제어회로도.1 is a conventional automatic balance level control circuit diagram.
제2도는 본 고안 자동 발란스 레벨 제어회로도.2 is an automatic balance level control circuit of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
Q1-Q7: 트랜지스터 PD : 수광다이오드Q 1 -Q 7 : Transistor PD: Photodiode
R1-R4: 저항 Vref : 기준전압R 1 -R 4 : Resistance Vref: Reference voltage
PIN : 포시티브입력단자 NIN : 네가티브입력단자PIN: positive input terminal NIN: negative input terminal
본 고안은 바이폴라 전지증폭기입력단의 자동 발란스 레벨 제어회로에 관한 것으로, 특히 리모콘 전지증폭기의 입력단에 삽입하여 형광등불빛등 기타 직류노이즈신호에 의한 오동작을 방지하기 위한 자동 발란스 제어회로에 관한 것이다.The present invention relates to an automatic balance level control circuit of a bipolar battery amplifier input stage, and more particularly, to an automatic balance control circuit inserted into an input terminal of a remote control battery amplifier to prevent a malfunction caused by a fluorescent lamp light or other DC noise signal.
종래의 자동 발란스 레벨 제어회로는 첨부된 도면 제1도에 도시된 바와 같이 기준전압(Vref)에 의해 온-오프 스위칭되는 트랜지스터(Q1)의 콜레터가 전원단자(Vcc)에 연결되고 그 트랜지스터(Q1)의 에미터는 전류원(IC1)에 연결됨과 아울러 저항(R1)을 통해 트랜지스터(Q2)의 베이스와 수광다이오드(PD)의 캐소우드, 전지증폭기의 포시티브입력단자(PIN) 및 트랜지스터(Q4)의 콜렉터에 연결되고, 상기 트랜지스터(Q1)의 에미터는 직렬연결된 다이오드(D1) 및 저항(R2)과 이와 병렬 연결된 저항(R1)을 통해 트랜지스터(Q4)의 에미터에 공통접속된 후 그 트랜지스터(Q1)의 베이스가 전지증폭기의 네가티브 입력단자(NIN) 및 트랜지스터(Q3)의 베이스에 연결되며, 상기 트랜지스터(Q2)(Q3)의 콜렉터는 에미터가 전원단자(Vcc)에 공통접속된 트랜지스터(Q5)(Q6)의 콜렉터에 연결됨과 아울러 그 트랜지스터(Q2)(Q3)의 에미터가 공통접속되어 전류원(IC2)에 연결구성되어 있다.In the conventional automatic balance level control circuit, a collet of a transistor Q 1 , which is switched on and off by a reference voltage Vref, is connected to a power supply terminal Vcc as shown in FIG. The emitter of (Q 1 ) is connected to the current source (IC 1 ), and through the resistor (R 1 ), the base of the transistor (Q 2 ), the cathode of the photodiode (PD), the positive input terminal (PIN) of the battery amplifier. and is connected to a collector of the transistor (Q 4), the emitter of series-connected diode of the transistor (Q 1) (D 1) and resistor (R 2) and this parallel-connected resistor (R 1) a transistor (Q 4) through the after the common connection to the emitter is connected to the base of the transistor (Q 1) a negative input terminal (NIN) and a transistor (Q 3) of the base cell amplifier, a collector of the transistor (Q 2) (Q 3) Is the transistor Q 5 (Q 6 ) where the emitter is commonly connected to In addition, the emitters of the transistors Q 2 and Q 3 are connected in common and connected to the current source IC 2 .
이와 같이 구성된 종래 자동 발란스 레벨제어회로는 먼저 기준전압(Vref)이 트랜지스터(Q1)의 베이스에 인가되고, 전지증폭기의 네가티브입력단자(NIN)로부터 출력된 로우전위가 트랜지스터(Q3)(Q4)의 베이스에 인가되면 트랜지스터(Q3)는 오프되고, 트랜지스터(Q1)(Q4)는 턴-온된다.In the conventional automatic balance level control circuit configured as described above, the reference voltage Vref is first applied to the base of the transistor Q 1 , and the low potential output from the negative input terminal NIN of the battery amplifier is applied to the transistor Q 3 (Q). When applied to the base of 4 ), transistor Q 3 is turned off and transistor Q 1 (Q 4 ) is turned on.
이에 따라 전원단자(Vcc)의 전압이 상기 트랜지스터(Q1)를 통해 전류원(IC1)으로 바이패스됨과 아울러 저항(R1)을 통해 트랜지스터(Q2)의 베이스와 전지증폭기의 포시티브입력단자(PIN) 및 수광다이오드(PD)의 캐소우드에 인가되므로 상기 트랜지스터(Q2)가 턴-온되어 전원단자(Vcc)의 전압이 트랜지스터(Q5)(Q2)를 통해 전류원으로 바이패스되며, 또한 상기 트랜지스터(Q1)를 통한 전원단자(Vcc)의 전압이 직렬연결된 다이오드(D1)와 저항(R1) 및 이와 병렬연결된 저항(R3)을 통하고, 다시 전지증폭기의 네가티브입력단자(NIN)에 의해 턴-온된 트랜지스터(Q4)를 통해 수광다이오드(PD) 및 전지증폭기의 포시티브입력단자(PIN)에 인가된다.Accordingly, the power supply terminal (Vcc) voltage of the current source (IC 1) to by-pass as soon addition Posey capacitive input terminal of the base and the cell amplifier transistor (Q 2) via a resistor (R 1) through the transistor (Q 1) of (PIN) and a light receiving diode, so applied to the cathode of the (PD) the transistor (Q 2) is turned on so that the voltage of the power supply terminal (Vcc) by-pass, and a current source via a transistor (Q 5) (Q 2) In addition, the voltage of the power supply terminal (Vcc) through the transistor (Q 1 ) through the diode (D 1 ) and the resistor (R 1 ) connected in series and the resistor (R 3 ) connected in parallel thereto, and again the negative input of the battery amplifier The transistor Q 4 is turned on by the terminal NIN and applied to the positive input terminal PIN of the photodiode PD and the battery amplifier.
이때 전지증폭기의 포시티브입력단자(PIN)의 전압은 수광다이오드(PD)에 전류가 없을 경우에 상기 트랜지스터(Q1)의 에미터로 흐르는 전압과 동일하게 유지되다가 수광다이오드(PD)에 전원단자(Vcc)의 전류가 흐르게 되면 그에 따라 포시티브입력단자(PIN)의 전압이 변화하게 된다.At this time, the voltage of the positive input terminal PIN of the battery amplifier is kept the same as the voltage flowing to the emitter of the transistor Q 1 when there is no current in the light receiving diode PD and then the power supply terminal of the light receiving diode PD. When the current of (Vcc) flows, the voltage of the positive input terminal (PIN) changes accordingly.
즉, 포시티브입력단자(PIN)의 전압 Vp = V1- (I0·R1)이 된다. (여기서, V1은 트랜지스터(Q1)의 에미터에 흐르는 전압이고, I0는 수광다이오드(PD)의 전류이다).That is, the voltage Vp = V 1- (I 0 · R 1 ) of the positive input terminal PIN becomes. (V 1 is a voltage flowing to the emitter of the transistor Q 1 , and I 0 is a current of the photodiode PD).
이와 같은 동작에서 외부로부터 큰 잡음신호 (예 : 형광등불빛 및 기타 직류노이즈)가 수광다이오드(PD)에 입력되어 그 수광다이오드(PD)의 전류가 한계이상 흐르게되면 포시티브입력단자(PIN)가 한계전압이하로 떨어져 전지증폭기가 오동작을 하게 되는 문제점이 있었다.In this operation, when a large noise signal (for example, fluorescent light and other DC noise) is inputted to the photodiode PD and the current of the photodiode PD flows above the limit, the positive input terminal PIN is limited. There was a problem that the battery amplifier malfunctioned to fall below the voltage.
본 고안은 이와 같은 종래의 문제점을 감안하여 전지증폭기의 네가티브입력단자에 PNP 형 트랜지스터를 추가하여 네가티브입력전압의 전류에 따른 변화폭을 줄여 외부잡음신호에 의한 오동작을 방지하도록 자동 발란스 레벨 제어회로를 안출한 것으로, 이하 본 고안을 첨부한 도면에 의거 상세히 설명하면 다음과 같다.In consideration of such a conventional problem, the present invention adds a PNP type transistor to the negative input terminal of the battery amplifier to reduce the change of the negative input voltage according to the current, thereby generating an automatic balance level control circuit to prevent malfunction by an external noise signal. If it is described in detail based on the accompanying drawings of the present invention as follows.
제2도는 본 고안 자동 발란스 레벨 제어회로도로서, 이에 도시한 바와 같이, 기준전압(Vref)에 의해 온-오프스위칭되는 트랜지스터(Q1)의 콜렉터를 전원단자(Vcc)에 연결하고, 그 트랜지스터(Q1)의 에미터는 전류원(IC1)에 연결함과 아울러 저항(R1)을 통해 트랜지스터(Q2)의 베이스와 수광다이오드(PD)의 캐소우드, 전지증폭기의 포시티브입력단자(PIN) 및 트랜지스터(Q4)(Q5)의 콜렉터에 공통접속하고, 상기 트랜지스터(Q1)의 에미터를 직렬연결된 저항(R2)(R4) 및 이와 병렬뎐결된 저항(R3)을 통해 트랜지스터(Q5)(Q4)의 에미터에 각기 연결하되 그 저항(R2)(R4)의 접속점을 트랜지스터(Q4)의 베이스에 연결한 후 그 트랜지스터(Q5)의 베이스를 전지증폭기의 네가티브입력단자(NIN) 및 트랜지스터(Q3)의 베이스에 연결하며 상기 트랜지스터(Q2)(Q3)의 콜렉터는 에미터가 전원단자(Vcc)에 공통접속된 트랜지스터(Q6)(Q7)의 콜렉터에 연결함과 아울러 그 트랜지스터(Q2)(Q3)의 에미터를 공통접속한 후 전류원(IC2)에 연결하여 구성한다.FIG. 2 is an automatic balance level control circuit of the present invention. As shown in the drawing, the collector of the transistor Q 1 on-off-switched by the reference voltage Vref is connected to the power supply terminal Vcc, and the transistor ( The emitter of Q 1 ) is connected to the current source IC 1 , and through the resistor R 1 , the base of the transistor Q 2 , the cathode of the photodiode PD, and the positive input terminal PIN of the battery amplifier. And a common connection to the collector of transistors Q 4 and Q 5 , through which the emitter of transistor Q 1 is connected through a series connected resistor R 2 and R 4 and a resistor R 3 connected in parallel thereto. Connect to the emitters of transistors Q 5 and Q 4 , respectively, and connect the connection points of the resistors R 2 and R 4 to the base of transistor Q 4 , and then connect the base of the transistor Q 5 to the battery. connected to the base of the negative input terminal (NIN) and a transistor (Q 3) of the amplifier and of the transistor (Q 2) (Q 3) The collector is connected to the collector of transistors Q 6 and Q 7 commonly connected to the power supply terminal Vcc, and the collector is connected to the emitter of transistors Q 2 and Q 3 . It is configured by connecting to IC 2 ).
이와 같이 구성된 본 고안의 적용, 효과를 상세히 설명하면 다음과 같다.When explaining the application, the effect of the present invention configured as described above in detail.
먼저 기준전압(Vref)이 트랜지스터(Q1)의 베이스에 인가되고, 전지증폭기의 네가티브입력단자(NIN)로부터 출력된 로우전위가 트랜지스터(Q3)(Q5)의 베이스에 인가되면 트랜지스터(Q3)는 오프되고, 트랜지스터(Q1)(Q5)는 턴-온된다.First, the reference voltage Vref is applied to the base of the transistor Q 1 , and when the low potential output from the negative input terminal NIN of the battery amplifier is applied to the base of the transistor Q 3 (Q 5 ), the transistor Q 3 ) is turned off and transistor Q 1 (Q 5 ) is turned on.
이에 따라 전원단자(Vcc)의 전압이 상기 트랜지스터(Q1)를 통해 전류원(IC1)으로 바이패스됨과 아울러 저항(R1)을 통해 트랜지스터(Q2)의 베이스와 전지증폭기의 포시티브입력단자(PIN) 및 수광다이오드(PD)의 캐소우드에 인가되므로 상기 트랜지스터(Q2)가 턴-온되어 전원단자(Vcc)의 전압이 트랜지스터(Q6)(Q2)를 통해 전류원(IC2)으로 바이패스되며, 또한 상기 트랜지스터(Q1)를 통한 전원단자(Vcc)이 전압이 직렬연결된 저항(R2)(R4)을 통하고 다시 전지증폭기의 네가티브입력단자(NIN)에 의해 톤-온된 트랜지스터(Q5)를 통해 수광다이오드(PD) 및 전지증폭기의 1에 인가됨과 아울러 저항(R3)을 통해 트랜지스터(Q4)의 에미터에 인가되나, 상기 트랜지스터(Q4)는 저항(R2)을 통한 하이전위에 의해 오프된다.Accordingly, the power supply terminal (Vcc) voltage of the current source (IC 1) to by-pass as soon addition Posey capacitive input terminal of the base and the cell amplifier transistor (Q 2) via a resistor (R 1) through the transistor (Q 1) of therefore applied to the cathode of (PIN) and the light-receiving diode (PD) the transistor (Q 2) is turned on so that the voltage of the power supply terminal (Vcc) via a transistor (Q 6) (Q 2) a current source (IC 2) And the power supply terminal (Vcc) through the transistor (Q 1 ) is passed through a resistor (R 2 ) (R 4 ) in series with the voltage and is again toned by the negative input terminal (NIN) of the battery amplifier. It is applied to the light-emitting diode PD and the cell amplifier 1 through the turned-on transistor Q 5 and to the emitter of the transistor Q 4 through the resistor R 3 , but the transistor Q 4 is applied to the resistor ( Off by the high potential through R 2 ).
따라서 상기 수광다이오드(PD) 및 전지증폭기의 포시티브입력단자(PIN)에 흐르는 전류는 다음과 같다.Therefore, the current flowing through the positive input terminal PIN of the photodiode PD and the battery amplifier is as follows.
이에 따라 외부로부터 큰 잡음신호가 수광다이오드(PD)에 입력되어 그 수광다이오드(PD)의 전류가 한계이상 흐르게 되더라도 포시티브입력단다(PIN)에는 일정전압이 유지되므로 전지증폭기가 정상동작을 하게 된다.Accordingly, even when a large noise signal is input from the outside to the light-emitting diode PD and the current of the light-emitting diode PD flows above the limit, a constant voltage is maintained at the positive input terminal PIN, so the battery amplifier operates normally. .
이상에서 상세히 설명한 바와 같이 본 고안은 전지증폭기의 입력단에 PNP형 트랜지스터를 추가하여 네가티브입력전압의 전류에 따른 변화폭을 줄여 줌으로써 외부잡음신호에 의한 전지증폭기의 오동작을 방지하게 된다.As described in detail above, the present invention adds a PNP-type transistor to an input terminal of the battery amplifier, thereby reducing a change in amplitude according to the current of the negative input voltage, thereby preventing malfunction of the battery amplifier due to an external noise signal.
즉, 전지증폭기의 네가티브입력단에 영향을 주는 부분을 저전위 전류로 고정해두고, 큰 전류를 네가티브입력전압에 영향을 주지 않는 PNP 트랜지스터로 흐르게 함으로써 전체 바이어스가 안정화되는 효과가 있다.That is, the overall bias is stabilized by fixing a portion that affects the negative input terminal of the battery amplifier to a low potential current and allowing a large current to flow through the PNP transistor that does not affect the negative input voltage.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910004530U KR960005180Y1 (en) | 1991-04-03 | 1991-04-03 | Automatic Balance Level Control Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910004530U KR960005180Y1 (en) | 1991-04-03 | 1991-04-03 | Automatic Balance Level Control Circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920020368U KR920020368U (en) | 1992-11-17 |
| KR960005180Y1 true KR960005180Y1 (en) | 1996-06-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019910004530U Expired - Lifetime KR960005180Y1 (en) | 1991-04-03 | 1991-04-03 | Automatic Balance Level Control Circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960005180Y1 (en) |
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1991
- 1991-04-03 KR KR2019910004530U patent/KR960005180Y1/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| KR920020368U (en) | 1992-11-17 |
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