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KR950030264A - 반도체소자 금속배선 형성방법 - Google Patents

반도체소자 금속배선 형성방법 Download PDF

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Publication number
KR950030264A
KR950030264A KR1019940007662A KR19940007662A KR950030264A KR 950030264 A KR950030264 A KR 950030264A KR 1019940007662 A KR1019940007662 A KR 1019940007662A KR 19940007662 A KR19940007662 A KR 19940007662A KR 950030264 A KR950030264 A KR 950030264A
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South Korea
Prior art keywords
tungsten nitride
film
nitride film
contact opening
deposition
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KR1019940007662A
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English (en)
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KR970005684B1 (ko
Inventor
김영선
박병률
박영욱
김용태
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김광호
삼성전자 주식회사
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Priority to KR1019940007662A priority Critical patent/KR970005684B1/ko
Publication of KR950030264A publication Critical patent/KR950030264A/ko
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Publication of KR970005684B1 publication Critical patent/KR970005684B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체소자의 금속배선 형성방법이 개시되어 있다. 실리콘 기판상의 콘택 개구부에 오믹 층인 티타늄막을 형성하고, 상기 티타늄막 위에서, NH3플라즈마 처리를 하고, 상기 NH3플라즈마 처리된 티타늄막상에 확산 방지막인 텅스텐 질화막을 플라즈마 화학증착법으로 형성한다.
플라즈마 화학증착법으로 텅스텐 질화막을 형성함으로써 단차도포성이 향상되고, 티타늄막을 형성함으로써 기판과 오믹 특성을 갖게되며, NH3플라즈마 처리를 실시함으로써 TiF3의 생성이 억제되어 콘택 저항을 감소시킨다.

Description

반도체소자 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3A도 내지 제3F는 본 발명에 의한 금속배선 형성방법의 일 예를 설명하기 위한 단면도들이고; 제4도는 본 발명에 따르는 티타늄막과 실리콘 기판과의 콘택 특성을 측정한 그래프이다.

Claims (16)

  1. 실리콘 기판상의 콘택 개구부에 티타늄을 증착하여 티타늄막을 형성하는 단계; 상기 티타늄막 형성후 NH3플라즈마 처리를 실시하는 단계; 상기 NH3플라즈마 처리된 티타늄막 위에 질화 텅스텐을 화학기상 증착 방법으로 증착하여 텅스텐 질화막을 형성하는 단계;를 구비하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  2. 제1항에 있어서, 상기 텅스텐 질화막 위에 금속을 증착하여 금속층을 형성하고 상기 금속층을 열처리하여 리플로우 시키는 단계를 더 구비하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  3. 제2항에 있어서, 상기 금속은 알루미늄(Al), 알루미늄합금, 구리(Cu), 금(Au), 은(Ag), 몰리브덴(Mo), 코발트(Co) 및 텅스텐(W)으로 구성된 군에서 선택된 어느 하나인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  4. 제3항에 있어서, 상기 알루미늄합금은 알루미늄-1%실리콘 또는 알루미늄-0.5% 구리-1%실리콘인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  5. 제1항에 있어서, 상기 화학기상증착방법은 플라즈마 화학기상증착방법인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  6. 제1항에 있어서, 상기 NH3플라즈마 처리는 300∼400℃의 증착온도, 90∼110W의 RF power, 0.05∼0.15Torr의 증착압력하에서 실시하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  7. 제6항에 있어서, 상기 증착온도는 350℃이고, 상기 RF power는 100W이고, 상기 증착압력은 0.1 Torr인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  8. 제1항에 있어서, 상기 텅스텐 질화막은 200∼450℃의 증착온도, 30∼400W의 RF power, 0.05∼0.3 Torr의 증착압력하에서 형성하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  9. 제8항에 있어서, 상기 증착온도는 350℃이고, 상기 RF power는 100W이고, 상기 증착압력은 0.1 Torr인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  10. 제1항에 있어서, 상기 콘택 개구부의 크기는 0.25㎛ 이상인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  11. 제2항에 있어서, 상기 텅스텐질화막 형성시 상기 텅스텐 질화물로 상기 콘택 개구부를 매몰시키는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  12. 제11항에 있어서, 상기 콘택 개구부의 크기는 0.25㎛ 이하인 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  13. 제2항에 있어서, 상기 티타늄막 형성시 상기 티타늄 막을 콘택 개구부의 바닥부분에만 형성하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  14. 제13항에 있어서, 상기 텅스텐 질화막 증착 후 상기 텅스텐 질화막의 에치 백(etch back)을 실시하여 상기 텅스텐 질화막으로 콘택 개구부를 매몰하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  15. 제1항에 있어서, 상기 텅스텐질화물로 콘택 개구부를 매몰시키고 상기 텅스텐질화막을 배선층으로 사용하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
  16. 제1항 또는 제2항에 있어서, 상기 텅스텐 질화막 증착후 400℃ 이상의 온도에서 열처리를 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019940007662A 1994-04-12 1994-04-12 반도체소자 금속배선 형성방법 KR970005684B1 (ko)

Priority Applications (1)

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KR1019940007662A KR970005684B1 (ko) 1994-04-12 1994-04-12 반도체소자 금속배선 형성방법

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KR1019940007662A KR970005684B1 (ko) 1994-04-12 1994-04-12 반도체소자 금속배선 형성방법

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KR950030264A true KR950030264A (ko) 1995-11-24
KR970005684B1 KR970005684B1 (ko) 1997-04-18

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100248804B1 (ko) * 1996-12-30 2000-03-15 김영환 반도체 소자의 금속 배선 형성방법
KR100266871B1 (ko) * 1996-06-28 2000-10-02 김영환 반도체 소자의 베리어 금속층 형성 방법
KR100430682B1 (ko) * 1996-12-31 2004-07-12 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
KR100510465B1 (ko) * 1998-05-12 2005-10-24 삼성전자주식회사 반도체장치의 배리어 금속막 형성방법
KR100525903B1 (ko) * 1998-06-05 2006-01-12 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100266871B1 (ko) * 1996-06-28 2000-10-02 김영환 반도체 소자의 베리어 금속층 형성 방법
KR100248804B1 (ko) * 1996-12-30 2000-03-15 김영환 반도체 소자의 금속 배선 형성방법
KR100430682B1 (ko) * 1996-12-31 2004-07-12 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
KR100510465B1 (ko) * 1998-05-12 2005-10-24 삼성전자주식회사 반도체장치의 배리어 금속막 형성방법
KR100525903B1 (ko) * 1998-06-05 2006-01-12 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법

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