[go: up one dir, main page]

KR950025913A - Micro pattern formation method of semiconductor device - Google Patents

Micro pattern formation method of semiconductor device Download PDF

Info

Publication number
KR950025913A
KR950025913A KR1019940001954A KR19940001954A KR950025913A KR 950025913 A KR950025913 A KR 950025913A KR 1019940001954 A KR1019940001954 A KR 1019940001954A KR 19940001954 A KR19940001954 A KR 19940001954A KR 950025913 A KR950025913 A KR 950025913A
Authority
KR
South Korea
Prior art keywords
oxide film
pattern
mask
forming
field oxide
Prior art date
Application number
KR1019940001954A
Other languages
Korean (ko)
Inventor
함영목
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940001954A priority Critical patent/KR950025913A/en
Publication of KR950025913A publication Critical patent/KR950025913A/en

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 공지의 기술로 게이트산화막을 갖는 필드산화막을 형성하고 그 상부에 상기 필드산화막이 노출되도록 오픈마스크를 형성한 후, 상기 필드산화막이 소자분리 역할을 할 수 있는 한도내에서 필드산화막을 습식방법으로 식각하여 단차를 완화시키고 상부의 오픈 마스크를 제거한다음, 그 상부에 도전층을 증착하고 전체구조상부에 감광막을 도포한 후, 미세패턴을 형성할 수 있는 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 도전층과 게이트산화막을 식각한 다음, 상부의 감광막패턴을 제거함으로써, 넛칭의 문제점이 대두되지 않으며 후속공정을 용이하게 하여 반도체소자의 수율을 향상시키는 기술이다.The present invention relates to a method for forming a fine pattern of a semiconductor device, and after forming a field oxide film having a gate oxide film by a known technique and forming an open mask to expose the field oxide film thereon, the field oxide film serves as device isolation. To the extent possible, the field oxide film is etched by a wet method to alleviate the step, the open mask on the upper part is removed, a conductive layer is deposited on the upper part, a photosensitive film is applied on the entire structure, and then a fine pattern is formed. By forming a photoresist film pattern which can be used as a mask, and etching the conductive layer and the gate oxide film using the photoresist pattern as a mask, and then removing the upper photoresist pattern, the problem of quenching does not arise and the subsequent process is facilitated so that the yield of a semiconductor device is facilitated. Is a technique to improve.

Description

반도체소자의 미세패턴 형성방법Micro pattern formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명의 실시예에 의해 반도체소자의 미세패턴 형성공정을 도시한 단면도.2A to 2F are cross-sectional views showing a micropattern forming process of a semiconductor device in accordance with an embodiment of the present invention.

Claims (1)

반도체기판 상부에 공지의 기술로 활성영역에 게이트산화막이 형성된 필드산화막을 형성하는 공정과, 전체 상부구조에 포지티브형 감광막을 도포하고 마스크를 사용하여 버즈빅이 노출되지 않도록 상기 필드산화막을 노출시키는 감광막패턴을 형성하여 오픈 마스크로 사용하는 공정과, 상기 오픈 마스크를 식각장벽으로하여 습식방법으로 상기 필드산화막을 식각하여 소자분리를 할 수 있는 한도내에서 단차를 완화시키는 공정과, 상기 오픈 마스크를 제거한 후, 전체구조상부에 도전층을 증착하고 그 상부에 감광막을 도포하고 마스크를 사용하여 노광 및 현상공정으로 미세패턴을 형성하기위한 감광막패턴을 형상하는 공정과, 상기 감광막패턴을 마스크로하여 도전층과 게이트산화막을 식각하여 도전층패턴과 게이트산화막패턴을 형성하고 상기 감광막패턴을 제거하는 공정을 포함하는 반도체소자의 미세패턴 형성방법.Forming a field oxide film having a gate oxide film formed in an active region on a semiconductor substrate by a known technique; and applying a positive photoresist film to the entire upper structure and exposing the field oxide film to expose the field oxide film by using a mask. Forming a pattern and using it as an open mask, Etching the field oxide layer by a wet method using the open mask as an etch barrier, and alleviating the step within the limit to allow device isolation, and removing the open mask. Thereafter, a conductive layer is deposited on the entire structure, a photoresist film is applied on the upper part of the structure, and a photoresist pattern for forming a micropattern is formed by an exposure and development process using a mask, and a conductive layer using the photoresist pattern as a mask. And the gate oxide film are etched to form a conductive layer pattern and a gate oxide pattern. A method of forming a fine pattern of a semiconductor device comprising the step of removing the photosensitive film pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001954A 1994-02-03 1994-02-03 Micro pattern formation method of semiconductor device KR950025913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940001954A KR950025913A (en) 1994-02-03 1994-02-03 Micro pattern formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940001954A KR950025913A (en) 1994-02-03 1994-02-03 Micro pattern formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR950025913A true KR950025913A (en) 1995-09-18

Family

ID=66663524

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940001954A KR950025913A (en) 1994-02-03 1994-02-03 Micro pattern formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR950025913A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970052784A (en) * 1995-12-07 1997-07-29 김주용 Field oxide film planarization method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970052784A (en) * 1995-12-07 1997-07-29 김주용 Field oxide film planarization method of semiconductor device

Similar Documents

Publication Publication Date Title
KR960005864A (en) Fine pattern formation method
KR0122315B1 (en) Micro-patterning method of semiconductor
KR950025913A (en) Micro pattern formation method of semiconductor device
KR960019522A (en) Plug Formation Method for Semiconductor Devices
KR980006032A (en) Method of forming an isolation region of a semiconductor device
KR100365752B1 (en) Method for forming contact hole in semiconductor device
KR100564746B1 (en) Method for manufacturing tee gate of compound semiconductor device
KR960014056B1 (en) Pattern forming method of potosensitive film
KR940016920A (en) Manufacturing method of bottom gate thin film transistor
KR940004725A (en) Contact hole formation method using step relief mask
KR950021063A (en) Step coverage improvement method of semiconductor device
KR950015577A (en) Manufacturing method of semiconductor device
KR940010199A (en) Reverse contact manufacturing method of semiconductor device
KR940016439A (en) Contact Forming Method of Semiconductor Device
KR970003482A (en) Contact hole formation method of semiconductor device
KR970052317A (en) Method for forming micro contact window of semiconductor device
KR970003561A (en) Fine pattern formation method
KR930006839A (en) Micro Pattern Formation Method in Semiconductor Manufacturing Process
KR940016671A (en) Method of forming resist pattern for silicide
KR960026303A (en) Fine pattern formation method
KR950001918A (en) Gate pattern forming method using nitride film
KR950021096A (en) Contact hole formation method of semiconductor device
KR960005791A (en) Contact hole formation method of semiconductor device
KR940016804A (en) Capacitor Formation Method of Semiconductor Device
KR970052301A (en) Gate electrode formation method of semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19940203

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid