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KR950022423A - Data Transmission Method in Multiprocessor System - Google Patents

Data Transmission Method in Multiprocessor System Download PDF

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Publication number
KR950022423A
KR950022423A KR1019930029348A KR930029348A KR950022423A KR 950022423 A KR950022423 A KR 950022423A KR 1019930029348 A KR1019930029348 A KR 1019930029348A KR 930029348 A KR930029348 A KR 930029348A KR 950022423 A KR950022423 A KR 950022423A
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KR
South Korea
Prior art keywords
processor
memory
boards
data
board
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Application number
KR1019930029348A
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Korean (ko)
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KR970001622B1 (en
Inventor
기안도
심원세
한종석
윤석한
송용호
Original Assignee
양승택
재단법인 한국전자통신연구원
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Priority to KR1019930029348A priority Critical patent/KR970001622B1/en
Publication of KR950022423A publication Critical patent/KR950022423A/en
Application granted granted Critical
Publication of KR970001622B1 publication Critical patent/KR970001622B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

본 발명은 복수의 프로세서 보드 (1,1a,1b,…,1m)와 복수의 메모리보드 (2,2a,2b,…,2m)사이에서 데이타와 어드레스 및 제어신호를 전송통로를 하는 시스템버스(3)가 접속되어 있고, 상기 프로세서 보드 각각은 프로세서를 구비하고 있고, 서로에 대해서는 독립적으로 데이타를 전송하기 위한 요청신호를 상기 메모리보드로 제공하며, 상기 메모리보드의 각각의 할당되어 있는 신호선(15,15a,15b,…,15m)를 포함하는 메모리상태선(16)을 부가한 다중 프로세서 시스템의 데이타 전송방법에 관한 것으로, 그 방법은 상기 각 프로세서 보드가 상기 신호선을 참조하여 데이타요청시기를 결정하여 재시도를 감소시키는 것을 특징으로 한다.The present invention provides a system bus for transmitting data, addresses, and control signals between a plurality of processor boards (1, 1a, 1b, ..., 1m) and a plurality of memory boards (2, 2a, 2b, ..., 2m). 3) are connected, each of the processor boards includes a processor, and provides a request signal for transmitting data independently to each other to the memory board, and each of the assigned signal lines 15 of the memory board. And a data transfer method of a multiprocessor system including a memory state line 16 including 15a, 15b, ..., 15m, wherein each processor board refers to the signal line to determine a data request time. To reduce retries.

Description

다중 프로세서 시스템의 데이타 전송방법Data Transmission Method in Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 정보교환의 통로로서 버스를 기본으로 하는 종래의 다중 프로세서 시스템의 구조를 보인 회로도.1 is a circuit diagram showing the structure of a conventional multiprocessor system based on a bus as a channel for information exchange.

제2도는 제1도에서 버스점유형 전송방식에 따라 데이타가 전송되도록 하는 어드레스 및 제어신호의 타이밍도.FIG. 2 is a timing diagram of an address and a control signal for transmitting data in accordance with a bus-type transfer scheme in FIG.

제3도는 제1도에서 파이프라인형 전송방식에 따라 데이타가 전송되도록 하는 어드레스 및 제어신호의 타이밍도.3 is a timing diagram of an address and a control signal for transmitting data according to the pipelined transmission scheme in FIG.

제4도는 본 발명의 데이타전송방법을 구현할 수 있는 다중프로세서 시스템의 구성을 보여주는 회로도.4 is a circuit diagram showing the configuration of a multiprocessor system capable of implementing the data transfer method of the present invention.

제5도는 제1도의 시스템에서 본 발명의 데이타전송방법을 보여주는 흐름도.5 is a flowchart showing a data transmission method of the present invention in the system of FIG.

Claims (2)

복수의 프로세서 보드(1,1a,1b,…,1m)와 복수의 메모리보드(2,2a,2b,…,2m)사이에서 데이타와 어드레스 및 제어신호를 전송통로를 하는 시스템버스(3)가 접속되어 있고, 상기 프로세서 보드 각각은 프로세서를 구비하고 있고, 서로에 대해서는 독립적으로 데이타를 전송하기 위한 요청신호를 상기 메모리보드로 제공하며, 상기 메모리보드의 각각의 할당되어 있는 신호선(15,15a,15b,…,15m)를 포함하는 메모리상태선(16)을 부가한 다중 프로세서 시스템의 데이타 전송방법에 관한 것으로, 그 방법은 상기 각 프로세서 보드가 상기 신호선을 참조하여 데이타요청시기를 결정하여 재시도를 감소시키는 것을 특징으로 하는 다중 프로세서 시스템의 데이타 전송방법.The system bus 3 which transmits data, address and control signals between the plurality of processor boards 1, 1a, 1b, ..., 1m and the memory boards 2, 2a, 2b, ..., 2m Each of the processor boards is provided with a processor, and provides a request signal for transmitting data independently to each other to the memory board, and each of the assigned signal lines 15, 15a, A data transfer method of a multiprocessor system in which a memory state line 16 including 15b, ..., 15m is added, and the method is used by each processor board to determine a data request timing with reference to the signal line and retry. Data transmission method of a multi-processor system, characterized in that for reducing. 제1항에 있어서, 상기 메모리상태선(16)이 상기 시스템버스에 포함되어 있는 것을 특징으로 하는 다중 프로세서 시스템의 데이타 전송방법.2. The method of claim 1, wherein said memory status line (16) is included in said system bus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930029348A 1993-12-23 1993-12-23 Method to improve transmission efficiency in the pipe-line type system bus KR970001622B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930029348A KR970001622B1 (en) 1993-12-23 1993-12-23 Method to improve transmission efficiency in the pipe-line type system bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930029348A KR970001622B1 (en) 1993-12-23 1993-12-23 Method to improve transmission efficiency in the pipe-line type system bus

Publications (2)

Publication Number Publication Date
KR950022423A true KR950022423A (en) 1995-07-28
KR970001622B1 KR970001622B1 (en) 1997-02-11

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KR1019930029348A KR970001622B1 (en) 1993-12-23 1993-12-23 Method to improve transmission efficiency in the pipe-line type system bus

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KR970001622B1 (en) 1997-02-11

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