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KR950021594A - 반도체 소자의 래치-업 방지장치 - Google Patents

반도체 소자의 래치-업 방지장치 Download PDF

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Publication number
KR950021594A
KR950021594A KR1019930031919A KR930031919A KR950021594A KR 950021594 A KR950021594 A KR 950021594A KR 1019930031919 A KR1019930031919 A KR 1019930031919A KR 930031919 A KR930031919 A KR 930031919A KR 950021594 A KR950021594 A KR 950021594A
Authority
KR
South Korea
Prior art keywords
latch
diode
substrate
junction
semiconductor device
Prior art date
Application number
KR1019930031919A
Other languages
English (en)
Inventor
박근우
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930031919A priority Critical patent/KR950021594A/ko
Publication of KR950021594A publication Critical patent/KR950021594A/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 OV미만의 기판 전압이 인가되는 기판과 접지 전압선(Vss)사이에 다이오드를 설치하여 입력 패드로부터 유입된 과전류를 접지 전압선으로 방전시키므로써, 반도체 소자에 래치-업이 발생하는 것을 방지한 장치에 관한 기술이다.

Description

반도체 소자의 래치-업 방지장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 통상의 입력보호 회로도
제2도는 제1도의 제조단면 구성도
제3도는 본 발명을 씨모스 회로의 일반적인 래치-업 모델에 적용한 실시예도.

Claims (2)

  1. ESD(Electro-Static Discharge) 입력 보호회로로 두꺼운 산화막 모스펫을 사용하는 반도체 소자에 있어서, 패드로부터 유입된 과도한 전류에 의해 기판 전압이 상승하여 래치-업(latch-up)이 발생하는 것을 방지하기 위하여, 소자의 각 패드 근처에 기판에서 접지 전압선(Vss)로 전류를 도통시키는 다이오드를 설치하여 기판전압이 래치-업 모델의 P-N+접합의 문턱전압을 넘지 못하도록 하는 것을 특징으로 하는 래치-업 방지장치.
  2. 제1항에 있어서, 상기 다이오드를 메탈콘택과 P-웰 접합함으로 형성함으로써, P-N+접합의 문턱 전압보다 더 낮은 문턱전압을 갖는 다이오드를 실현하는 것을 특징으로 하는 래치-업 방지장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930031919A 1993-12-31 1993-12-31 반도체 소자의 래치-업 방지장치 KR950021594A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031919A KR950021594A (ko) 1993-12-31 1993-12-31 반도체 소자의 래치-업 방지장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031919A KR950021594A (ko) 1993-12-31 1993-12-31 반도체 소자의 래치-업 방지장치

Publications (1)

Publication Number Publication Date
KR950021594A true KR950021594A (ko) 1995-07-26

Family

ID=66853799

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930031919A KR950021594A (ko) 1993-12-31 1993-12-31 반도체 소자의 래치-업 방지장치

Country Status (1)

Country Link
KR (1) KR950021594A (ko)

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Patent event code: PA01091R01D

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Patent event date: 19931231

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Patent event date: 19931231

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Patent event date: 19970312

Patent event code: PE09021S01D

E601 Decision to refuse application
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Patent event date: 19970618

Comment text: Decision to Refuse Application

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Patent event date: 19970312

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Patent event code: PE06011S01I