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KR950004409A - Via Contact Hole Formation Using Plasma Device - Google Patents

Via Contact Hole Formation Using Plasma Device Download PDF

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Publication number
KR950004409A
KR950004409A KR1019930013690A KR930013690A KR950004409A KR 950004409 A KR950004409 A KR 950004409A KR 1019930013690 A KR1019930013690 A KR 1019930013690A KR 930013690 A KR930013690 A KR 930013690A KR 950004409 A KR950004409 A KR 950004409A
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South Korea
Prior art keywords
chf
gas
contact hole
frequency electrode
polymer
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Application number
KR1019930013690A
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Korean (ko)
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KR960015486B1 (en
Inventor
양대근
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문정환
금성일렉트론 주식회사
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Priority to KR1019930013690A priority Critical patent/KR960015486B1/en
Publication of KR950004409A publication Critical patent/KR950004409A/en
Application granted granted Critical
Publication of KR960015486B1 publication Critical patent/KR960015486B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 제조공정에서 플라즈마 장치를 이용한 비아-콘택홀(7) 형성방법에 관한 것으로, 층간 절연막을 SOG(4)로 형성하였을 경우, 에칭시 언더컷이 발생하는 것을 방지하기 위해, Ar+CHF3+CF4가스를 이용하여 초기 에칭을 수행한 후, 오버에치 하기전 고주파 전극의 전원을 차단하고 CHF3가스만을 반응로에 주입하여 SOG(4)막 보호층에서 전표면상에 2차 폴리머를 형성하고, 반응로에 Ar+CHF3가스를 10-20 : 1 비율로 주입하면서 오버-에치 공정을 수행하여 SOG막(4)의 언더컷 현상을 방지하여, 콘택금속 형성시 콘택금속의 끊어짐을 방지할 수 있다.The present invention relates to a method for forming a via-contact hole (7) using a plasma device in a semiconductor manufacturing process. When the interlayer insulating film is formed of SOG (4), in order to prevent undercut during etching, Ar + CHF After the initial etching was performed using 3 + CF 4 gas, the high frequency electrode was turned off before overetching, and only CHF 3 gas was injected into the reactor, so that the secondary polymer was formed on the entire surface of the SOG (4) film protective layer. And over-etch process while injecting Ar + CHF 3 gas into the reactor at a ratio of 10-20: 1 to prevent undercut of the SOG film 4 to prevent breakage of the contact metal when forming the contact metal. It can prevent.

Description

플라즈마 장치를 이용한 비아(Via)콘택홀 형성방법Via contact hole formation method using plasma device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도(A)-(D)는 본 발명의 비아-콘택홀 형성공정 단면도, 제4도는 제3도에 의한 비아-콘택홀 형성후 콘택금속 증착 단면도이다.3A to 3D are cross-sectional views of a via-contact hole forming process of the present invention, and FIG. 4 is a cross-sectional view of deposition of contact metal after via-contact hole formation according to FIG.

Claims (4)

반도체 기판(1) 상에 금속패턴(2), 제1절연막(3), SOG(4), 제2절연막(5)이 차례로 형성되고, 제2절연막(5) 상에 금속패턴(2)의 상측 일정폭이 패턴된 감광막(6)이 형성된 샘플에 비아-콘택홀을 형성하는 방식에 있어서, 상기 샘플을 플리즈마 장치의 고주파 전극에 장착하고 반응로에 Ar+CHF3+CF4가스를 주입하면서 고주파 전극에 전원을 인가하여 에칭되는 비아-콘택홀(7)의 측벽에 제1폴리머(8a)를 형성하면서 초기에칭하는 제1단계 공정, 제1단계 공정후, 고주파 전극의 전원을 차단하고, CHF3가스를 일정시간 동안 주입하여 제2폴리머(8b)를 노출된 전표면에 형성하면서 제2단계 공정, 제2단계 공정후, 다시 고주파 전극에 전원을 인가하고, CHF3+Ar 가스를 주입하여 비아 콘택홀(7)의 측벽에 제3폴리머(8c)를 형성하면서 오버-에치하는 제3단계 공정으로 이루어짐을 특징으로 하는 플라즈마 장치를 이용한 비아(Via)콘택홀 형성방법.The metal pattern 2, the first insulating film 3, the SOG 4, and the second insulating film 5 are sequentially formed on the semiconductor substrate 1, and the metal pattern 2 is formed on the second insulating film 5. In the method of forming a via-contact hole in a sample on which the upper constant width patterned photosensitive film 6 is formed, the sample is mounted on the high frequency electrode of the plasma apparatus and Ar + CHF 3 + CF 4 gas is injected into the reactor. While applying the power to the high-frequency electrode to form a first polymer (8a) on the sidewall of the via-contact hole (7) to be etched after the first step, the first step after the first step process, the power of the high frequency electrode is cut off After injecting CHF 3 gas for a predetermined time to form the second polymer 8b on the exposed entire surface, power is supplied to the high frequency electrode again after the second step process and the second step process, and the CHF 3 + Ar gas is supplied. And a third step of over-etching the third polymer 8c on the sidewall of the via contact hole 7 by injection. A via (Via) The method of forming contact holes using a plasma apparatus as ranging. 제1항에 있어서, 3단계 공정에서 Ar과 CHF3의 가스비를 10-20 : 1로 함을 특징으로 하는 플라즈마 장치를 이용한 비아(Via)콘택홀 형성방법.The method of claim 1, wherein the ratio of Ar to CHF 3 is set to 10-20: 1 in a three step process. 제1항에 있어서, 제1, 2절연막(3, 5)은 산화막으로 형성함을 특징으로 하는 플라즈마 장치를 이용한 비아(Via)콘택홀 형성방법.The method of claim 1, wherein the first and second insulating films (3, 5) are formed of an oxide film. 제1항에 있어서, 제2폴리머(8b)는 200-300Å의 두께로 형성함을 특징으로 하는 플라즈마 장치를 이용한 비아(Via)콘택홀 형성방법.The method of claim 1, wherein the second polymer (8b) is formed to a thickness of 200-300 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930013690A 1993-07-20 1993-07-20 Via contact hole forming method using plasma apparatus KR960015486B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930013690A KR960015486B1 (en) 1993-07-20 1993-07-20 Via contact hole forming method using plasma apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930013690A KR960015486B1 (en) 1993-07-20 1993-07-20 Via contact hole forming method using plasma apparatus

Publications (2)

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KR950004409A true KR950004409A (en) 1995-02-18
KR960015486B1 KR960015486B1 (en) 1996-11-14

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100413042B1 (en) * 1995-12-19 2004-03-12 주식회사 하이닉스반도체 Micro contact hole formation method of semiconductor device
KR100454926B1 (en) * 1997-01-14 2005-04-13 삼성전자주식회사 How to install the maintenance program of the exchange
KR100510740B1 (en) * 2000-12-21 2005-08-30 주식회사 하이닉스반도체 Method for wiring metal layer in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100413042B1 (en) * 1995-12-19 2004-03-12 주식회사 하이닉스반도체 Micro contact hole formation method of semiconductor device
KR100454926B1 (en) * 1997-01-14 2005-04-13 삼성전자주식회사 How to install the maintenance program of the exchange
KR100510740B1 (en) * 2000-12-21 2005-08-30 주식회사 하이닉스반도체 Method for wiring metal layer in semiconductor device

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Publication number Publication date
KR960015486B1 (en) 1996-11-14

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