KR950001510B1 - Frame processing module - Google Patents

Abstract

None.

Description

Frame processing module

1 is a block diagram of a frame processing module according to the present invention.

2 is a signal waveform diagram between a frame processing module and an ISDN T.A according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 3: MUX 2, 4: DEMUX

5: MFP 6: CPU

7: address decoder and central timing unit

8: ROM 9: RAM

10: DMAC 11, 12: buffer

13: PC Card 14: PC Bus I / F

15: PC Parallel I / F 16: LED Display

17: Status register 18: Serial communication I / F

19, 20, 31: RS-232 I / F 21, 22: V.35 I / F

23: RS-449 I / F 24: loopback control

25: T.A 26, 27: SDSU

28: Audio codec I / F 29: Still picture codec I / F

30: Motion video codec I / F 32: OSC

The present invention relates to a frame processing module (FPM) capable of simultaneously providing voice, video and data communication services through a digital subscriber network.

Existing terminals mainly provide video, voice, and data communication services in independent forms, and thus exist as voice terminals (telephones), video terminals (video phones, FAX), and data communication terminals.

However, by multiplexing the service information in the H.221 frame and simultaneously transmitting them through the digital subscriber line, the utilization of the line can be increased and a single function terminal (video phone, video conferencing device) can provide various services. Induce development.

Currently, in developed countries, IC chips in accordance with CCITT Recommendation H.221 have been commercialized as part of a video phone-related chipset.

The present invention provides a frame processing module that provides video, voice, and data communication services using H.221 multiplexer and demultiplexer developed as a semiconductor chip and provides an H.242 communication control procedure function for providing the service. The purpose is.

In order to achieve the above object, the present invention provides a frame processing module that can apply voice, video, and data communication services through a digital subscriber network, comprising: a network interface, a serial communication control interface, and a serial communication interface. Interface means for performing a switching and loopback control function between the first and second MUXs connected to the interface means and multiplexing all data transmitted from the source codec in an H.221 frame structure to a network, and DEMUX, Address bus and data bus connected to the first and second MUX and DEMUX, multi frame peripheral (MFP) connected to the address bus and data bus, CPU connected to the address bus and data bus, DMAC connected to the address bus and data bus ( Direct memory access controller), the address bus and the data bus It characterized in that the configuration to the connected first and second buffers, the address bus and a data bus connected to the PC parallel interface, a PC card connected to the PC parallel interface, and PC bus interface connected to the PC card.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a frame processing module according to the present invention, 1 and 3 are MUX (Multiplexer), 2 and 4 are Demultiplexer (DEMUX), 5 is a Multi-Frame Peripheral (MEP), and 6 is a Central Processing Unit (CPU). 7 is an address decoder and central timing unit, 8 is a read only memory (ROM), 0 is a random access memory (RAM), 10 is a direct memory access controller (DMAC), 11 is a buffer, 13 is a PC card, 14 PC bus I / F (Interface), 15 PC parallel I / F, 16 LED display, 17 status register, 18 serial communication I / F, 19, 20, 31 are RS 232 I / F, 21 22 is V.35 I / F, 23 is RS-449 interface, 24 is loopback control, 25 is TA 26 and 27 are SDSU, 28 is Audio Codec Interface (I / F), 29 is Still Picture Codec I / C, 30 is Motion Video Codec Interface (I / F) And 32 represent OSC (Oscillator), respectively.

MUX1 (1), DEMUX1,2 (2,4), slave MUX2 (3), MPF (5), CPU (6), address decoder and central timing unit (7), ROM (8), which are masters according to the present invention. , RAM (9), DMAC (10), buffers (11, 12), PC card (13), PC busless decoder and central timing unit (7), ROM (8), RAM (9), DMAC (0) , Buffers 11, 12, PC card 13, PC buses 19, 20, 31, V.35 I / F (21, 22), RS-449 interface 23, loopback controller 24, Audio codec I / F 28, Still Picture Codec I / F 29, Motion Video Codec I / F 30, and OSC 32 It is composed.

The interface unit serial communication I / F (18), audio codec I / F (28), still picture codec I / F (29) connected to the MUX 1, 2 (1, 3) and DEMUX 1, 2 (2, 4), And a motion video codec I / F 30, the serial communication I / F 18, an audio codec I / F 28, a still picture codec I / F 29, and a motion video codec I / F 30. RS-232 I / F (19, 20), RS-449 interface (23), loopback control unit 24, SDSU (26, 27) and codec I / F (28, 29, 30) connected to the It consists of V.35 I / F (21, 22) connected to serial communication I / F (18) to provide network interface and serial communication control interface, and performs switching function and loopback control between various serial interfaces.

The MUX1,2 (1,3) and DEMUX1,2 (2,3) are motion video with the serial communication I / F 18, audio codec I / F 28, and still picture codec I / F 29. It is connected to the codec I / F 30, the address bus and the data bus, and functions to multiplex all data transmitted from the source codec into an H.221 frame structure and access the network.

The CPU 6, the ROM 8, the RAM 9, the OSC 32, the address decoder and the central timing unit 7 are connected to the address bus and the data bus to control frame processing module control and communication control procedure and PC. It has a file transfer function. The CPU 6 uses Motorola's 6800 CPU as a preferred embodiment.

The MFP 5 is connected to an address bus and a data bus, and provides an interface with a console terminal to download and execute an application program during module development. The MFP 5 provides interrupts from a PC and MUX / DEMUX (1, 2, 3, Generates an interrupt from 4).

The DMAC 10 is connected to an address bus and a data bus to perform a high speed data transfer function between the memory and the memory.

The buffers 11 and 12 temporarily store data from the PC parallel I / F 15 to the file transfer service between PCs and send the data to the MUXs 1 and 3 or send data from the DEMUXs 2 and 4. It is temporarily stored and sent to the PC parallel I / F 15 and has a capacity of 2K × 8 bits.

The PC parallel interface 15 provides the transmission path of the PC data together with the buffers 11 and 12, exchanges command and message information between the VCT driving program and the frame processing module software, and processes interrupts.

The PC card 13 is connected to the PC parallel I / F 15 and the PC bus I / F 14 and performs a function for an interface between the PC bus I / F 14 and the frame processing module.

The LED display unit 16 functions to visually inform the operating state of the module, and the state register 17 is a bus error and an interrupt state of MUX1,2 / DEMUX1,2 (1,2,3,4,). Can be polled.

Source codec input and output interfaces include Serial Input from Motion Video Codec Module (MVCMSI), Serial Input from Still Picture Codec Module (SPCMSI), Serial Input from Audio Codec Module (ACMSI), Serial Input from Application Channel FIFO (ACSI), and Serial MVCMSO (MVCMSO). It consists of Output from Motion Video Codec Module, SPCMSO (Serial Output from Still Picture Codec Module), ACMSO (Serial Output from Codec Module) and ACSO (Serial Output from Application Channel FIFO).

Here, the data stored in the frame processing module transmission buffer 11 can be transmitted through the application channel (6.4 Kbps) of the ACSO H.221 frame of the multiplexer, and the received data from the ACSI of the demultiplexer is stored in the reception buffer 12. . The data of the transmission buffer 11 is transmitted from the PC through the PC bus interface 14, and the data of the reception buffer 12 is received by the PC through the PC bus interface 14. In other words, a channel is formed between the PC and the frame process module through which the appropriate data information can be transmitted and received through the transmission buffers 11 and 12.

Application channels can be up to 300bps, depending on the application. Motion video codecs, still picture codecs, and audio codecs can transmit up to 62.4 Kbps data rates over call-free still image voice information through a transmission buffer similar to the data information path.

2 is a signal waveform diagram between the frame processing module and the ISDN T.A 25 according to the present invention, and illustrates an interface process between the RS-232 I / Fs 19 and 20 and the ISDN network.

The present invention, which is configured and operated as described above, synchronizes the B-channels of the H.221 multiplexer and the demultiplexer by using a delay RAM and an appropriate control circuit, and uses a digital network connection (ISDN TA or SDSU) of multiple channels. When connected, it is possible to communicate in various communication modes through 1B to 6B connection, 1HO to 5HO connection, or H11 and H12 connection, and the application effects are as follows.

First, to provide services in the fields of high quality telephone, voice and video conferencing, audio graphic, etc., which can service voice, video, and data by multiplexing, a network access device that can accommodate such services in various modes. Second, since it consists of two H.221 multiplexer / demultiplexer pairs and two single B-channels, the synchronization between channels is not considered and 1B to 6B connection is provided when synchronization between channels is not considered. Service is available through 1HO to 5HO connection or H11 and H12 connection.

Claims (4)

A frame processing module, which can apply voice, video, and data communication services through a digital subscriber network; An interface means for performing switching and loopback control functions between the network interface and the serial communication control interface, and a serial communication interface, and multiplexing all data transmitted from the source codec to the H.221 frame structure and accessing the network. First and second MUX (1,3) and DEMUX (2,4), address bus and data bus connected to the first and second MUX and DEMUX (2,4), connected to the address bus and data bus Multi Frame Peripheral (MEP) 5, a CPU 6 connected to the address bus and a data bus, a Direct Memory Access Controller (DMAC) 10 connected to the address bus and a data bus, and a connection to the address bus and a data bus. A first and second buffers 11 and 12, a PC parallel interface 15 connected to the address bus and a data bus, a PC card 13 connected to the PC parallel interface 15, The frame processing module, characterized in that consisting of a PC bus interface (14) connected to the PC card 13. The frame processing module according to claim 1, further comprising an LED display means (16) connected to the address bus and the data bus to visually inform the operating state of the module. 2. Status register means (17) according to claim 1, connected to said address bus and data data bus for polling a bus error and interrupt status of said first and second MUX (1,3) and DEMUX (2,4). Frame processing module, characterized in that further comprises. The serial communication interface (18) according to any one of claims 1 to 3, wherein the interface means is connected to the first and second MUX and DEMUX (1, 2, 3, 4). Audio codec interface 28 connected to second MUX and DEMUX 1, 2, 3, 4, and still picture codec interface 29 connected to the first and second MUX and DEMUX 1, 2, 3, 4. A motion video codec interface 30 connected to the first and second MUXs and DEMUXs 1, 2, 3, and 4, the serial communication interface 18, the audio codec interface 28, and the still picture codec interface 29 And the first and second RS-232 interfaces 19 and 20 connected to the motion video codec interface 30, the serial communication interface 18, the audio codec interface 28, the still picture codec interface 29, and the motion. First and second V.35 interfaces 21 and 22 connected to an audio codec interface 30, the serial communication interface 18 and an audio codec RS-449 interface 23 connected to interface 28, still picture codec interface 29, and motion video codec interface 30, said serial communication interface 18, audio codec interface 28, and still picture codec interface And a loopback control means (24) connected to the motion audio codec interface (30).