KR950001301B1 - Device Separation Method of Semiconductor Device - Google Patents
Device Separation Method of Semiconductor Device Download PDFInfo
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- KR950001301B1 KR950001301B1 KR1019920000157A KR920000157A KR950001301B1 KR 950001301 B1 KR950001301 B1 KR 950001301B1 KR 1019920000157 A KR1019920000157 A KR 1019920000157A KR 920000157 A KR920000157 A KR 920000157A KR 950001301 B1 KR950001301 B1 KR 950001301B1
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- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000000926 separation method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 28
- 238000002955 isolation Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 210000003323 beak Anatomy 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
내용없음.None.
Description
제1도는 종래의 방법에 의하여 형성된 소자분리영역의 단면도.1 is a cross-sectional view of an isolation region formed by a conventional method.
제2a~c도는 본 발명에 의한 소자분리방법을 나타내는 공정순서도.2a to c is a process flow chart showing a device isolation method according to the present invention.
제3a~d도는 본 발명에 따른 소자분리방법의 일실시예를 나타내는 공정순서도이다.3a to d are process flowcharts showing an embodiment of the device isolation method according to the present invention.
본 발명은 반도체 장치의 소자 분리 방법에 관한 것으로, 보다 상세하게는 필드 산화막의 형상 각도를 조절하여 소자의 동작 특성을 개선하기 위한 반도체 장치의 소자 분리 방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device for improving the operating characteristics of the device by adjusting the shape angle of the field oxide film.
반도체 소자가 고집적화됨에 따라 소자 분리 기술에서도 소자 분리 영역이 줄어들고 있으며, 널리 사용되고 로코스(LOCOS : local oxidation of silicon)법을 이용하면 필드 산화막 성장시 버드비크(bird's beak)가 너무 크게 자라 고밀도 반도체 장치의 활성 영역을 축소하는데 악영항을 미치고, 두 활성 영역 사이의 펀치쓰루 현상을 방지하기 위하여 과도하게 채널저지 이온 주입하면 접합 누설전류가 크ㄹ게 증가하면 MOS트랜지스터의 소폭효과(narrow width effect)가 크게 증대하는 등 여러가지 문제점이 발생하여 이러한 문제점을 해결하기 위한 다양한 방안이 강구되어 왔다.As semiconductor devices have been highly integrated, device isolation areas have been reduced, and widely used and local oxidation of silicon (LOCOS) methods have caused the bird's beak to grow too large when growing field oxide films. To reduce the active area of the MOS transistor, and excessive channel blocking ion implantation to prevent the punch-through phenomenon between the two active areas, a large increase in the junction leakage current results in a narrow width effect of the MOS transistor. Various problems have occurred, such as greatly increasing, and various methods have been devised to solve these problems.
그 방법중의 하나로 R-LOCOS(recessed-LOCOS)법에 의한 구조가 두 활성 영역 사이의 펀치쓰루 현상을 막기 위하여 제안되었다. 상기 구조에서 버드비크의 크기를 줄일 경우 필드 산화막의 경사가 매우 급하게 되어 필드 산화막 성장 및 희생 산화막 제거 공정을 실시하면 필드 산화막과 활성영역의 경계면이 매끄럽지 못한 문제가 있다.As one of the methods, a structure by the recessed-LOCOS (R-LOCOS) method has been proposed to prevent the punch-through phenomenon between two active regions. When the size of the bud beak is reduced in the above structure, the inclination of the field oxide film becomes very sharp, and when the field oxide film growth and the sacrificial oxide film removing process are performed, the interface between the field oxide film and the active region is not smooth.
제1도는 R-LOCOS법에 의하여 형성된 소자분리영역의 단면도를 나타낸 것으로 패드 산화막 대신 옥시나이트라이드막(oxinitride layer)(2)을 사용하여 필드 산화막(4)을 성장시킨 것이다. 옥시나이트라이드막은 특성상 산화종의 확산을 방지하기 때문에 버드비크는 거의 발생하지 않으나 필드산화막과 활성 영역의 경계면에서 필드 산화막의 기판에 대한 각도(θ)가 90이하가 되어 이후 산화막 식각공정에서 활성영역이 매끈하지 못하여 게이트 산화막의 신뢰성을 저하시킴에 따라 반도체 반도체의 동작을 특성에 악영향을 미치는 등 문제점이 발생한다. 참조 부호 1은 반도체 기판을, 3은 질화막을 각각 나타낸다.1 shows a cross-sectional view of an isolation region formed by the R-LOCOS method, in which a field oxide film 4 is grown by using an oxynitride layer 2 instead of a pad oxide film. Because oxynitride film prevents the diffusion of oxidized species due to its characteristics, Budbeek hardly occurs, but the angle (θ) of the field oxide film to the substrate is less than 90 at the interface between the field oxide film and the active region. This lack of smoothness lowers the reliability of the gate oxide film, which causes problems such as adversely affecting the operation of the semiconductor semiconductor. Reference numeral 1 denotes a semiconductor substrate, and 3 denotes a nitride film.
따라서, 본 발명의 목적은 필드 산화막과 활성영역의 경계면을 매끄럽게 형성하여 게이트 산화막의 신뢰성을 증가시킬 수 있는 반도체 장치의 소자분리 방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device capable of increasing the reliability of the gate oxide film by smoothly forming the interface between the field oxide film and the active region.
본 발명에 따른 반도체 장치의 소자 분리 방법은, 반도체 기판상에 옥시나이트라이드막 및 질화막을 차례로 형성하는 단계, 사진 식각법으로 상기 질화막의 소정 부분을 표면으로부터 적어도 상기 옥시나이트라이드막까지 식각하여 개구부를 형성한 다음 상기 옥시나이트라이드막을 언더 커팅하는 단계, 그리고 열산화법으로 필드 산화막을 형성하는 단계를 포함한다.The device isolation method of the semiconductor device according to the present invention comprises the steps of sequentially forming an oxynitride film and a nitride film on a semiconductor substrate, by etching a predetermined portion of the nitride film from the surface to at least the oxynitride film by photolithography. And forming a field oxide film by thermal oxidation, followed by undercutting the oxynitride film.
본 발명의 상세한 내용은 첨부한 도면을 참고로 하여 아래에서 설명한다.Details of the present invention will be described below with reference to the accompanying drawings.
제2도(a) 내지 (c)는 본 발명에 따른 반도체 장치의 소자 분리 방법을 나타낸 공정순서도이다.2 (a) to 2 (c) are process flowcharts illustrating a device separation method of a semiconductor device according to the present invention.
제2도(a)에 도시한 바와 같이, 반도체 기판(21)상에 100~500Å 두께의 옥시나이트라이드막(22)과 1000~2000Å두께의 질화막(23)을 차례로 형성한다. 이때, 상기 옥시나이트라이드막(22)과 질화막(23)은 LPCVD(low pressure chemical deposition)법으로 형성하고 특히 상기 옥시나이트라이드막(22)은 NH3, SiH2Cl2및 N2O가스를 100~500mT의 압력과 600~800℃의 온도 조건에서 열분해하여 형성한다.As shown in FIG. 2A, an oxynitride film 22 having a thickness of 100 to 500 kPa and a nitride film 23 having a thickness of 1000 to 2000 kPa are sequentially formed on the semiconductor substrate 21. In this case, the oxynitride film 22 and the nitride film 23 are formed by low pressure chemical deposition (LPCVD), and in particular, the oxynitride film 22 may contain NH 3 , SiH 2 Cl 2, and N 2 O gas. It is formed by thermal decomposition under pressure of 100 ~ 500mT and temperature condition of 600 ~ 800 ℃.
다음, 일반적인 사진 식각법으로 상기 질화막(23)을 반도체 기판(21)까지 식각한 후, BOE(buffered oxide etchant)용액 등을 이용한 습식 식각법으로 옥시나이트라이드막(22)을 언더 커팅(under cutting)한다[제2도 (b)]. 상기 질화막(23)을 식각할 때 반도체 기판(21)의 일부를 식각하여 필드산화막의 매몰 깊이를 조절할 수 있으며 이때 기판이 식각되는 깊이는 0.05~0.2㎛정도이다. 또한 상기 옥시나이트라이드막(22)의 언더 컷의 크기를 필드 산화막의 형성에 영향을 주므로 0.1~0.3㎛정도로 하는 것이 필드 산화막의 형상 각도를 90이상이 되도록 하는데 바람직하다. 만약, 언더 컷의 깊이가 0.3㎛ 이상이 되면, 버드비크가 0.3㎛이상이 되어 서브미크론(submicron), 특히 0.5㎛ 이하의 장치에서는 실용성이 없다.Next, the nitride film 23 is etched to the semiconductor substrate 21 by a general photolithography method, and then the oxynitride film 22 is under cut by a wet etching method using a buffered oxide etchant (BOE) solution or the like. [FIG. 2 (b)]. When the nitride layer 23 is etched, a part of the semiconductor substrate 21 may be etched to adjust the depth of embedding of the field oxide layer, and the depth at which the substrate is etched is about 0.05 to 0.2 μm. In addition, since the size of the undercut of the oxynitride film 22 affects the formation of the field oxide film, it is preferable to set the shape angle of the field oxide film to 90 or more because it is about 0.1 to 0.3 µm. If the depth of the undercut is 0.3 µm or more, the bud beak becomes 0.3 µm or more, and there is no practical use in an apparatus of submicron, especially 0.5 µm or less.
마지막으로, 제2도(c)에 도시된 바와같이, 고온, 예를들어 1000℃에서 습식 산화법으로 3000~5000Å두께의 필드산화막(24)을 형성한다. 이때, 상술한 옥시나이트라이드막의 언더 컷 때문에 언더 컷의 크기 정도로 버드비크가 형성되며 필드 산화막의 형상각도(θ)는 90이상이 된다.Finally, as shown in FIG. 2C, a field oxide film 24 having a thickness of 3000 to 5000 kPa is formed by a wet oxidation method at a high temperature, for example, 1000 占 폚. At this time, due to the undercut of the oxynitride film described above, a bud beak is formed to the extent of the undercut, and the shape angle θ of the field oxide film is 90 or more.
이와 같은 소자분리 방법에 따르면 이후에 실시되는 희생산화막 제거공정 등에서 산화막이 식각되더라도 활성 영역의 가장자리에 네가티브슬로프(negative slope)가 형성되지 않으므로 게이트 산화막이 형성되더라도 전계가 집중되는 것을 방지할 수 있어 게이트 산화막의 신뢰성을 저하시키지 않는다.According to the device isolation method as described above, even when the oxide layer is etched in a subsequent sacrificial oxide removal process, a negative slope is not formed at the edge of the active region, thereby preventing the electric field from being concentrated even when the gate oxide layer is formed. It does not lower the reliability of the oxide film.
본 발명의 소자 분리 방법에 따른 다른 방법의 공정 순서도가 제3도(a) 내지 (d)에 도시되어 있다.A process flow diagram of another method according to the device isolation method of the present invention is shown in Figures 3 (a) to (d).
먼저, 제3도(a)에서 처럼, 반도체 기판(31)상에 100~500Å 두께의 옥시나이트라이드막(22) 및 1000~2000Å 두께의 질화막(33)을 차례로 형성한다. 이때에도 전술된 바와 같이 상기 옥시나이트라이드막(22)과 질화막(33)은 LPCVD법으로 형성하고 옥시나이트라이드막 역시 NH3, SiH2Cl8, N2O 가스를 100~500mT의 압력과 600~800℃의 온도 조건에서 열분해하여 형성한다.First, as shown in FIG. 3A, an oxynitride film 22 having a thickness of 100 to 500 kPa and a nitride film 33 having a thickness of 1000 to 2000 kPa are sequentially formed on the semiconductor substrate 31. As described in the foregoing wherein the oxynitride film 22 and nitride film 33 are formed in the LPCVD method and the oxynitride film also NH 3, SiH 2 Cl8, N 2 O gas of 100 ~ 500mT pressure and 600 to It is formed by thermal decomposition at a temperature of 800 ℃.
그후, 제3도(b)에 도시한 바와 같이, 사진 식각법을 이용하여 상기 질화막(33)을 상기 기판까지 식각하여 개구부를 형성한 후 BOE용액을 이용한 습식 식각법으로 상기 옥시나이트라이드막(22)의 언더 컷을 약0.1~0.2㎛의 깊이로 형성한다.Subsequently, as shown in FIG. 3 (b), the nitride film 33 is etched to the substrate using a photolithography method to form an opening, and then the oxynitride film is formed by a wet etching method using a BOE solution. An undercut of 22) is formed to a depth of about 0.1 to 0.2 mu m.
다음에, 기판 전표면 상에 500~1000Å 두께의 폴리실리콘층을 형성한 후 비등방성 식각하여 제3도(c)에 도시한 바와 같이 개구부 측벽에 스페이서(34)를 형성한다.Next, a polysilicon layer having a thickness of 500 to 1000 Å is formed on the entire surface of the substrate, and then anisotropically etched to form a spacer 34 on the sidewall of the opening as shown in FIG.
그후, 제3도(d)에 도시된 바와같이 고온에서 습식산화하여 필드 산화막(35)을 형성한다.Thereafter, as shown in FIG. 3 (d), by wet oxidation at a high temperature, a field oxide film 35 is formed.
본 실시예에서 폴리실리콘 스페이서(34)는 과도한 언더 커팅으로 인하여 버드비크가 커지는 것을 막는 역할을 하며, 옥시나이트라이드막 언더 컷이 형성되기 때문에 필드 산화막의 형상각도는 90이상으로 된다.In this embodiment, the polysilicon spacer 34 serves to prevent the bud beak from growing due to excessive undercutting, and since the oxynitride film undercut is formed, the shape angle of the field oxide film is 90 or more.
이와 같은 소자 분리 방법에 따르면 전술된 실시예에서와 마찬가지로 이후의 희생 산화막 제거 공정에서 산화막이 식각되더라도 활성영역의 가장자리에 네가티브 슬러프가 형성되지 않으므로 게이트 산화막이 형성되더라도 전계가 집중되는 현상을 피할 수 있어 게이트 산화막의 신뢰성을 저하시키지 않는 장점이 있다.According to the device isolation method as described above, even when the oxide film is etched in a subsequent sacrificial oxide removal process, negative slough is not formed at the edge of the active region, so that the electric field is concentrated even when the gate oxide film is formed. There is an advantage that does not lower the reliability of the gate oxide film.
이상의 실시예를 통해 알수 있는 바와같이, 본 발명의 소자 분리 방법에 의하면 필드 산화막의 형상각도가 90이상이 되므로 게이트 산화막의 신뢰성이 향상되며 MOS트랜지스터의 소폭을 제어할 수 있어 고집적 반도체 장치를 제조하는데 적합한 장점을 갖는다.As can be seen through the above embodiment, according to the device isolation method of the present invention, since the shape angle of the field oxide film is 90 or more, the reliability of the gate oxide film is improved, and the width of the MOS transistor can be controlled to manufacture the highly integrated semiconductor device. Has a suitable advantage.
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