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KR940017834A - Delay Compensation Circuit for Memory Access - Google Patents

Delay Compensation Circuit for Memory Access Download PDF

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Publication number
KR940017834A
KR940017834A KR1019920023603A KR920023603A KR940017834A KR 940017834 A KR940017834 A KR 940017834A KR 1019920023603 A KR1019920023603 A KR 1019920023603A KR 920023603 A KR920023603 A KR 920023603A KR 940017834 A KR940017834 A KR 940017834A
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KR
South Korea
Prior art keywords
signal
delay
address
delay amount
section
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KR1019920023603A
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Korean (ko)
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KR950013062B1 (en
Inventor
송기환
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이헌조
주식회사 금성사
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Priority to KR1019920023603A priority Critical patent/KR950013062B1/en
Priority to GB9311138A priority patent/GB2267590B/en
Priority to DE4317937A priority patent/DE4317937C2/en
Publication of KR940017834A publication Critical patent/KR940017834A/en
Priority to US08/366,402 priority patent/US5564039A/en
Application granted granted Critical
Publication of KR950013062B1 publication Critical patent/KR950013062B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/05—Synchronising circuits with arrangements for extending range of synchronisation, e.g. by using switching between several time constants

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

본 발명은 HDTV등의 기기에서 영상의 움직임을 보상하기 위하여 사용하는 두개 이상의 프레임 메모리를 액세스할 경우에 실제로 유효한 데이타를 번지지정하기 위하여 각기 상이한 지연 시간차를 보상하는 것으로서 종래에는 지연량을 수동으로 조절하는 것으로서 지연량을 조절할 경우에 사용자가 일일이 입력데이타를 변화시켜 맞추어야 됨은 물론 지연량이 변화될 경우마다 입력데이타를 다시 입력시켜야 되어 사용자에게 많은 번거로움을 주었고, 또한 지연량이 정확히 조절되었는지를 판별할수 없음은 물론 기기의 동작시 지연량이 변화되어도 이를 판별할수 없었다.The present invention compensates for the different delay time in order to address the effective data when accessing two or more frame memories used for compensating the motion of an image in a device such as an HDTV. Conventionally, the delay amount is manually adjusted. When the delay amount is adjusted, the user has to change the input data one by one, and the input data must be input again whenever the delay amount is changed, which causes a lot of trouble for the user and also cannot determine whether the delay amount is correctly adjusted. Of course, even if the amount of delay during the operation of the device could not be determined.

본 발명은 데이타 액세스 스타트 동기신호 및 기록데이타 입력동기신호와 시스템 클럭신호를 이용하여 지연량을 검출하고, 검출한 지연량을 판단하여 어드레스 신호의 출력을 지연시키는 지연 제어신호를 발생시키며, 발생시킨 지연 제어신호에 따라 어드레스 신호를 지연 출력함과 아울러 지연량의 보상동작을 표시하여 사용자에게 알림으로써 사용자가 일일이 입력데이타를 변화 입력시켜야 되는 번거로움을 제거하고, 지연량을 정확히 보상할수 있음은 물론 지연량의 변화가 있을 경우에 이를 사용자가 간단히 판별할수 있다.According to the present invention, a delay amount is detected using a data access start sync signal, a write data input sync signal, and a system clock signal, and a delay control signal for delaying output of an address signal is determined by determining the detected delay amount. By delaying outputting the address signal according to the delay control signal and displaying the compensation operation of the delay amount, the user can eliminate the inconvenience of having to input the input data individually and compensate the delay accurately. If there is a change in the delay amount, the user can easily identify it.

Description

메모리 액세스시 지연 보상회로Delay Compensation Circuit for Memory Access

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 지연보상회로의 전체구성을 보인 블록도, 제2도는 본 발명의 지연 보상회로의 지연량 검출부 및 동작표시부의 상세도, 제3도는 본 발명의 지연 보상회로의 지연제어부의 상세도, 제4도는 본 발명의 지연 부상회로의 어드레스 카운트부의 상세도.1 is a block diagram showing the overall configuration of the delay compensation circuit of the present invention, FIG. 2 is a detailed view of the delay amount detecting unit and the operation display unit of the delay compensation circuit of the present invention, and FIG. 3 is a delay control unit of the delay compensation circuit of the present invention. 4 is a detailed view of the address counting section of the delay floating circuit of the present invention.

Claims (5)

입력되는 데이타 액세스 스타트 동기신호(FSYNC) 및 기록데이타 입력동기신호(FSYNCW)로 지연량을 검출하는 지연량 검출부(1)와, 상기 지연량 검출부(1)의 출력신호로 지연량을 판단하여 어드레스 신호의 출력을 지연시키게 제어신호를 출력하는 지연제어부(2)와, 상기 기록데이타 입력동기신호(FSYNCW) 및 지연제어부(2)의 출력신호에 따라 지연량의 보상동작을 표시하는 동작표시부(3)와, 상기 지연제어부(2)의 출력신호에 따라 지연되면서 어드레스를 카운트하여 출력하는 어드레스 카운트부(4)와, 상기 어드레스 카운트부(4)의 출력신호에 따른 메모리의 동작으로 기록데이타 입력동기신호(FSYNCW) 및 데이타 액세스 스타트 동기신호(FSYNC)를 궤환시키는 지연변환 궤환부(5)로 구성함을 특징으로 하는 메모리 액세스시 지연 보상회로.The delay amount detection unit 1 detects the delay amount by the input data access start synchronization signal FSYNC and the recording data input synchronization signal FSYNCW, and the delay amount is determined by the output signal of the delay amount detection unit 1, and the address is determined. A delay control section 2 for outputting a control signal to delay the output of the signal, and an operation display section 3 for displaying a compensation operation of the delay amount in accordance with the output signal of the recording data input synchronization signal FSYNCW and the delay control section 2; ), An address counting unit 4 which counts and outputs an address while being delayed according to the output signal of the delay control unit 2, and synchronizes recording data input by operation of a memory according to the output signal of the address counting unit 4; And a delay conversion feedback section (5) for feeding back the signal (FSYNCW) and the data access start synchronization signal (FSYNC). 제1항에 있어서, 지연량 검출부(1)는, 데이타 액세스 스타트 동기신호(FSYNC) 및 기록데이타 입력동기신호(FSYNCW)를 배타적 논리합하여 지연차를 검출하는 익스클루시브 오아게이트(11)와, 데이타 액세스 스타트 동기신호(FSYNC)의 레벨변화를 검출하는 레벨변화 검출부(12)와, 상기 레베변화 검출부(12)의 출력신호에 따라 입력신호를 로드하고 상기 익스클루시브 오아게이트(11)의 출력신호에 따라 인에이블되면서 시스템 클럭신호(SCLK)를 카운트하여 지연량 검출신호로 출력하는 지연량 카운트부(13)로 구성함을 특징으로 하는 메모리 액세스시 지연 보상회로.2. The exclusive amount of the delayed detection unit (1) according to claim 1, wherein the delay amount detecting unit (1) includes an exclusive OR of the data access start synchronization signal (FSYNC) and the write data input synchronization signal (FSYNCW) to detect a delay difference; A level change detection unit 12 for detecting a level change of the data access start synchronization signal FSYNC, and an input signal in accordance with the output signal of the lever change detection unit 12, and outputting the exclusive oar gate 11; And a delay amount counting unit (13) which is enabled according to a signal and counts a system clock signal (SCLK) and outputs it as a delay amount detection signal. 제1항에 있어서, 지연제어부(2)는 데이타 액세스 스타트 동기신호(FSYNC)의 레벨변화를 검출하는 레벨변화 검출부(21)와, 상기 레벨변화 검출부(21)의 출력신호에 따라 지연량 검출부(1)의 출력신호를 로드하여 다운카운트하는 카운터(221,222)로 된 다운 카운트부(22)와, 상기 다운 카운트부(22)의 출력신호로 지연량에 따른 어드레스 발생 제어신호를 출력하는 제어신호 출력부(23)로 구성함을 특징으로 하는 메모리 액세스시 지연 보상회로.2. The delay control unit 2 according to claim 1, wherein the delay control unit 2 includes a level change detection unit 21 for detecting a level change of the data access start synchronization signal FSYNC, and a delay amount detection unit in accordance with an output signal of the level change detection unit 21. A down count unit 22 comprising counters 221 and 222 for loading and down counting the output signal of 1) and a control signal output for outputting an address generation control signal according to a delay amount as an output signal of the down count unit 22; A delay compensating circuit for memory access, comprising: a section (23). 제1항에 있어서, 동작표시부(3)는, 기록데이타 입력동기신호(FSYNCW)의 동기위치를 검출하는 동기위치 검출부(31)와, 지연량 검출부(2)의 출력신호를 카운트하는 제어신호 카운트부(32)와, 상기 동기위치 검출부(31) 및 제어신호 카운트부(32)의 출력신호로 지연보상된 동기신호의 동기를 비교하는 동기비교부(33)와, 상기 동기비교부(33)의 출력신호로 동기상태를 표시하는 표시부(34)로 구성함을 특징으로 하는 메모리 액세스시 지연 보상회로.The operation display unit (3) according to claim 1, wherein the operation display unit (3) includes a control signal count for counting the output signal of the synchronization position detection unit (31) for detecting the synchronization position of the recording data input synchronization signal (FSYNCW) and the delay amount detection unit (2). A synchronizing comparison section 33 for comparing the synchronization of the synchronizing signals delayed by the output signals of the synchronizing position detecting section 31 and the control signal counting section 32, and the synchronizing comparing section 33; And a display unit (34) for displaying a synchronization state with an output signal of the memory. 제1항에 있어서, 어드레스 카운트부(4)는 시스템 클럭신호(SCLK)를 카운트하여 어드레스 신호를 발생하는 카운터(441-419)로 된 어드레스 발생부(41)와, 상기 어드레스 발생부(41)가 발생한 어드레스 신호를 출력하는 버퍼(421,422)로 된 어드레스 출력부(42)와, 상기 어드레스 출력부(42)의 출력신호로 1블록의 어드레스 신호의 출력이 완료되는지를 판별하여 어드레스 카운트부(41)를 제어하는 앤드게이트(43)와, 상기 앤드게이트 및 지연제어부(2)의 출력신호에 따라 어드레스 카운트부(41)의 클리어를 제어하는 카운트 제어부(44)로 구성함을 특징으로 하는 메모리 액세스시 지연 보상회로.2. An address generator (4) according to claim 1, wherein the address counter (4) comprises an address generator (41) comprising a counter (441-419) for counting a system clock signal (SCLK) and generating an address signal. Address output section 42 including buffers 421 and 422 for outputting an address signal generated by the controller and whether the output of the address signal of one block is completed by the output signal of the address output section 42, and then the address counting section 41 ) And a count control section 44 for controlling the clearing of the address count section 41 according to the output signals of the AND gate and delay control section 2. Delay compensation circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920023603A 1992-05-29 1992-12-08 Delay compensation circuit for frame memory access KR950013062B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920023603A KR950013062B1 (en) 1992-12-08 1992-12-08 Delay compensation circuit for frame memory access
GB9311138A GB2267590B (en) 1992-05-29 1993-05-28 Memory access delay control circuit for image motion compensation
DE4317937A DE4317937C2 (en) 1992-05-29 1993-06-01 Memory access delay control circuit for image migration compensation
US08/366,402 US5564039A (en) 1992-05-29 1994-12-29 Memory access delay control circuit for image motion compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920023603A KR950013062B1 (en) 1992-12-08 1992-12-08 Delay compensation circuit for frame memory access

Publications (2)

Publication Number Publication Date
KR940017834A true KR940017834A (en) 1994-07-27
KR950013062B1 KR950013062B1 (en) 1995-10-24

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KR1019920023603A KR950013062B1 (en) 1992-05-29 1992-12-08 Delay compensation circuit for frame memory access

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US10533966B2 (en) 2017-07-27 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Digital time domain readout circuit for bioFET sensor cascades

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