JPH02165195A - Automatic adjusting system for display position - Google Patents

Abstract

PURPOSE:To eliminate a manual operation for correcting a display position by providing a counting means for counting the time required for generating a video signal from a horizontal synchronizing signal on a video adaptor. CONSTITUTION:The inside of a video adaptor is provided with a counting means for counting the time required for generating a video signal after a horizontal synchronizing signal is varied, a position storage means for storing the time required for generating the video signal after the horizontal synchronizing signal is varied, and a rewriting means for comparing a value of the counting means and a value of the display position storage means and executing a control for writing the value of the counting means in the display storage means, if the value of the counting means is smaller. The minimum value of the time required for generating the video signal from the horizontal synchronizing signal is always held, and by using this value, the display start position is determined. In such a way, the display start position on the display screen can be adjusted by a small number of hardwares.

Description

[Detailed Description of the Invention] [Summary] A configuration in which a flat display can be used instead of a CRT display by connecting a video adapter to a CRT controller connected to a personal computer or the like and providing the video adapter. In order to solve the problem of conventional technology that requires manual operation as a means of correcting the display position in a display system that is A counting means for counting, a display position storage means for storing the value of the counting means, a comparison circuit for comparing the value of the display position storage means and the value of the counting means, etc. are provided, thereby making manual operation for correcting the display position possible. It was designed to eliminate this.

[Industrial application field]

The present invention provides a display system in which a flat display can be used instead of a CRT display by connecting a video adapter to a CRT controller and providing the video adapter. can be adjusted automatically.

[Conventional technology]

FIG. 7 is a diagram showing an outline of a CRT-connected personal computer. In the figure, 1 is a central processing unit, 2 is a central processing unit;
is memory, 3 is CRT controller, 4 is CRT, *H
□ and *Vsync indicate a negative logic horizontal synchronization signal, and *Vsync indicate a negative logic vertical synchronization signal, respectively.

When the central processing unit 1 instructs the CRT controller 3 to display data, the CRT controller 3 converts the synchronization signals (*Hsync and *Viync) and video signals into CRs.
Send to T4.

By the way, when a user who used to use a CRT as a display device for a desktop computer such as a personal computer uses a flood display instead of a CRT for the purpose of saving space, it is generally a video display. A board called an adapter is inserted between the main unit and the flat display. FIG. 8 is a diagram showing an outline of a personal computer connected to a flat display. In the figure, 5 indicates a video adapter, and 6 indicates a flat display.

The video adapter 5 receives the *H□TIC+ mVg output from the CRT controller 3. and a video signal, and sends a synchronization signal, a video signal, and a shift clock to the flat display 6.

The flat display is a concept that includes liquid crystal displays, plasma displays, etc.

In the display system shown in FIG. 8, a lock signal required by the flat display 6 is generated by the video adapter 5, but it is also necessary to accurately determine the display start position. If this cannot be done accurately, it is necessary to correct (adjust the position) by hand.

Although the positional relationship between the horizontal synchronizing signal and the video signal is a fixed numerical value, it varies depending on factors such as variations in the elements of the CRT controller, so it differs from one main body to another.

If this is displayed as is on the display, the horizontal display position may shift by several dots to the left or right.

Therefore, it is necessary to move the display position to the normal position. FIG. 9 is a block diagram showing an example of a conventional video adapter. In the figure, 7 is an oscillator, 8 is a phase control circuit, 9 is a display position adjustment circuit, 10 is an adjustment switch, 11 is a latch circuit, and 12 is an AND gate.

The oscillator 7 is called a CO, and the oscillator 7 and the phase control circuit 8 constitute a PLL.

“HMynC” is input to the phase control circuit 8.
The display position adjustment circuit 9 has *Hmync and *Vsy. The display position adjustment circuit 9 outputs a synchronization signal to the flat display and a DSPEN signal (display enable signal).

An adjustment switch 10 is added to the display position adjustment circuit 9, and by operating the adjustment switch 10, "
) Adjust the time from the rise of Isyac to the rise of the DSPEN signal. In addition, in the display position adjustment circuit 9,
Although not shown, there are shift circuits, multiplexers, etc. The latch circuit 11 receives an inverted video signal (*Video
) is captured in synchronization with the dot clock output from the oscillator 7, and a video signal is sent to the flat display 6. The dot clock and the DSPEN signal are input to the AND gate 12. The output of AND gate 12 becomes shift clock 5CLK.

Further, as a method of bringing the display position to the normal position, for example, a method described in Japanese Patent Laid-Open No. 62-239190 is known. In this method, a microprocessor is installed in the video adapter, and the personal computer's V mVnc* H%YnC signal is compared with the counter up information independently specified by the microprocessor to determine whether or not it was specified correctly. This is a method of setting the specified parameter to the counter again as soon as it can be read.

[Problem to be solved by the invention]

In a display system using a video adapter as shown in Figure 9, in order to adjust the display start position on the display screen,
There was a drawback that the operator had to operate the adjustment switch while looking at the display screen, making it complicated to adjust the display start position.

Although the method disclosed in Japanese Patent Application Laid-Open No. 62-239190 has the advantage of being compatible with many personal computers, it also increases costs due to the use of a microprocessor, and also requires that the display not be displayed on the left side of the screen. If you have a screen like this, it has the disadvantage that it will be displayed left-justified and you will not be able to see the margins.

The present invention was created with this point in mind, and C
Connect the video adapter to the RT controller and connect the video adapter to the RT controller.
The purpose of this invention is to enable automatic adjustment of the display start position on the display screen with a small amount of hardware in a display system in which a flat display is connected to an adapter.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. The present invention is based on CRT
A display system is assumed that has a controller, a video adapter, and a flat display. C
The RT controller outputs a horizontal synchronization signal, a vertical synchronization signal, and a video signal.

The video adapter receives the horizontal synchronization signal, vertical synchronization signal, and video signal output from the CRT controller, and sends the synchronization signal, video signal, and shift clock to the flat display.

The video adapter has counting means, display position storage means, rewriting means, and shift clock generation means. The counting means counts the time from when the horizontal synchronizing signal changes until the video signal is output. The display position storage means stores the time from when the horizontal synchronizing signal changes until the video signal is output. The rewriting means compares the value of the counting means and the value of the display position storage means, and if the value of the counting means is smaller,
Control is performed to write the value of the counting means into the display position storage means. The shift clock generation means outputs the shift clock train after a time period determined by the value of the display position storage means has elapsed since the horizontal synchronization signal changed.

[Embodiment] FIG. 2 is a diagram showing an example of the configuration of a video adapter of the present invention. In the figure, 13 indicates an automatic adjustment circuit.

The automatic adjustment circuit 13 operates from the rise of Hsyac to *Vi.
The number of dot clocks until deo is detected is counted, and the minimum value of the number of dot clocks counted so far is output to the display position adjustment circuit 9. Assuming that the time equivalent to this minimum number of dot clocks is T□8, the display position adjustment circuit 9 sets DSPEN to 1 after T MIN time from the rise of $Hgync.

FIG. 3 is a diagram illustrating the generation of a dot clock according to the present invention. ``If the time T from the rise of Hsync to the fall of this video is the smallest so far, *H
Shift clock 5CLK after T time from the rise of □
is generated.

FIG. 4 is a block diagram of a configuration example of the automatic adjustment circuit of the present invention. In the figure, 14 is a flip-flop, and 15 is a flip-flop.
-1 and 15-2 are counter elements, 16-1 and 16-2 are comparison circuit elements, 17-1 and 17-2 are display position storage register elements, 18 is a MIN holding register, 19 is an AND gate, and 20 is a driver are shown respectively.

All parts 14 to 20 except for the display position adjustment circuit 9 are present in the automatic adjustment circuit 13.

Flip-flop 14 is initialized at the rising edge of the H5ync signal and outputs 1. A dot clock is applied to the flip-flop 14 as a clock, and *Video is applied as an input.

The output of the flip-flop 14 and the dot clock are input to the AND gate 19, and the output of the AND gate 19 is applied to the clock input of the counter element 15-1, 15-2.

Counter elements 15-1 and 15-2 constitute a counter. Counter elements 15-1 and 15-2 are each hexadecimal counters. Counter element 15-1.1
A pulse generated from the *)(,, fic signal) is applied to the clear terminal of counter element 15-2.
When 1 outputs a carry, 1 is applied to the enable terminal of counter element 15-2, and counter 15-2 becomes ready for counting.

Comparison circuit elements 16-1 and 16-2 constitute a comparison circuit. Data to be compared is input to the A input and B input of the comparison circuit element, and the comparison result from the previous stage is input to the C input. Display position storage register elements 17-1 and 17
-2 constitutes a display position storage register.

The comparison circuit compares the value of the counter with the value of the display position storage register. When the value of the counter is less than the value of the display position storage register, the MIN holding register 18 is set, thereby writing the value of the counter to the display position storage register. If the value of the counter is greater than the display position storage register, nothing is done. In this way, since the minimum value is held in the display position storage register, if this numerical value is used to determine the display position, there is no need for manual adjustment.

Figure 5 is a diagram showing the memory timing of the counter.*
” When Hsync falls, a comparison result detection timing signal is generated. When the value of the counter is smaller than the value of the display position storage register, a pulse is output from the comparison circuit, and this pulse is input to the MEN holding register,
A pulse is output from the MIN holding register, and the value of the counter is set in the display position storage register by this pulse.

FIG. 6 is a diagram showing a method of generating a shift clock.

The shift clock is generated by the display position adjustment circuit. "When Hsync rises, a counter initialization signal is generated, and the counter is initialized by this. The counter value is incremented by 1 every time a clock is generated. The counter value and the value of the display position storage register are They are compared by a comparator, and when the counter value is greater than or equal to the value in the display position storage register, the output of the comparator becomes 1, and when the output of the comparator becomes 1, the clock is output as a shift clock.

[Effects of the Invention] As is clear from the above description, according to the present invention, the minimum value of the time from the horizontal synchronization signal to the appearance of the video signal is always held in the display position storage register. If the display start position is determined using this method, a remarkable effect can be achieved in that there is no need to manually adjust the display start position.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram showing an example of the configuration of the video adapter of the present invention, FIG. 3 is a diagram explaining shift clock generation according to the present invention, and FIG. FIG. 5 is a diagram showing a configuration example of the automatic adjustment circuit of the invention. FIG. 5 is a diagram showing the memory timing of the counter. FIG. 6 is a diagram explaining the shift clock generation method. FIG. FIG. 8 is a diagram showing an outline of a personal computer connected to a flat display, and FIG. 9 is a diagram showing an example of the configuration of a conventional video adapter. 1...Central processing unit, 2...Memory, 3...CR
T controller, 4...CRT, *l(,,,,c,
...Horizontal synchronization signal of negative logic, "Vsync"...Vertical synchronization signal of negative logic, 5...Video adapter, 6...
Flat display, 7... Oscillator, 8... Phase control circuit, 9... Display position adjustment circuit, 10... Adjustment switch, 11... Latch circuit, 12... AN
D gate, 13... automatic adjustment circuit, 14... flip-flop, 15-1 and 15-2... counter element, 16-1 and 16-2... comparison circuit element, 17-1 and 17-2...Display position record register element, 1st day...
MIN holding register, 19...AND gate, 20.
··driver. This invention t＞@'vA boat cycle example 4-zusai 4 the furnace's beer child
Figure 0LK -11111go■----Danichiyu--Ohama 9th [;Depends on the shift clock S No. 31 yen] CRT 1's Hersoal Congo Yuk Figure 8 Ishiba Bundle of Bii “O.7 Rippukku No. 1”

Claims (1)

[Claims] A flat display; a CRT controller that outputs a horizontal synchronization signal, a vertical synchronization signal, and a video signal; and a synchronization system that receives and receives the horizontal synchronization signal, vertical synchronization signal, and video signal output from the CRT controller. In a display system comprising a video signal, a video signal, and a video adapter that sends a shift clock to a flat display, in the video adapter, from the time the horizontal sync signal changes until the video signal appears a counting means for counting the time of , a display position storage means for storing the time from when the horizontal synchronizing signal changes until the video signal is output, and comparing the value of the counting means and the value of the display position storage means; If the counting means is smaller, the rewriting means controls the writing of the value of the counting means into the display position storage means, and the rewriting means controls the writing of the value of the counting means into the display position storage means, and after the elapse of the time determined by the value of the display position storage means after the horizontal synchronization signal changes. , and shift clock generation means for outputting a shift clock train.