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KR940010393A - 티타늄 질화물과 폴리실리콘으로 구성되는 적층된 층들을 이용하는 게이트 전극 - Google Patents

티타늄 질화물과 폴리실리콘으로 구성되는 적층된 층들을 이용하는 게이트 전극 Download PDF

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Publication number
KR940010393A
KR940010393A KR1019930020478A KR930020478A KR940010393A KR 940010393 A KR940010393 A KR 940010393A KR 1019930020478 A KR1019930020478 A KR 1019930020478A KR 930020478 A KR930020478 A KR 930020478A KR 940010393 A KR940010393 A KR 940010393A
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KR
South Korea
Prior art keywords
gate
polysilicon
gate electrode
titanium nitride
central
Prior art date
Application number
KR1019930020478A
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English (en)
Inventor
황정모
폴락 고든
Original Assignee
윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리엄 이. 힐러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 윌리엄 이. 힐러
Publication of KR940010393A publication Critical patent/KR940010393A/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

게이트 산화물(2)와 MOSFET 게이트의 폴리실리콘부와의 사이에 끼인 중앙 밴드갭 일함수 물질(TiN)들은 CMOS 기술에 있어서 임계 전압의 정확도와 대칭에 관한 문제점을 해결한다.

Description

티타늄 질화물과 폴리실리콘으로 구성되는 적층된 층들을 이용하는 게이트 전극
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 양호한 제1실시예를 도시한 단면도,
제2도는 본 발명의 양호한 제2실시예를 도시한 단면도.

Claims (6)

  1. 게이트 산화물과 게이트를 사이에 끼인 중앙 밴드갭 반도체 물질을 함유하는 게이트를 포함하는 것을 특징으로 하는 MOSFET.
  2. 제1항에 있어서, 상기 중앙 밴드갭 물질이 TiN, Si-Ge, 티타늄 실리사이드 또는 이들의 조합물들로부터 선택되는 것을 특징으로 하는 MOSFET.
  3. 제1항에 있어서, 실리콘을 함유한 상기 게이트부가 다결정 실리콘을 포함하는 것은 특징으로 하는 MOSFET.
  4. 게이트 산화물과 게이트부 사이에 끼인 중앙 밴드갭 반도체 물질을 함유하는 게이트와 실리콘을 함유하는 상기 게이트부를 각각 갖고 있는 NMOS 트랜지스터와 PMOS 트랜지스터를 포함하는 것을 특징으로 하는 CMOS 디바이스.
  5. 제4항에 있어서, 상기 중앙 밴드갭 물질이 TiN, Si-Ge, 티타늄 실리사이드 또는 이들의 조합물들로부터 선택되는 것을 특징으로 라는 CMOS 디바이스.
  6. 제4항에 있어서, 실리콘을 함유한 상기 게이트부가 다결정 실리콘을 포함하는 것을 특징으로 하는 CMOS 디바이스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930020478A 1992-10-05 1993-10-05 티타늄 질화물과 폴리실리콘으로 구성되는 적층된 층들을 이용하는 게이트 전극 KR940010393A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US95614192A 1992-10-05 1992-10-05
US07/956,141 1992-10-05

Publications (1)

Publication Number Publication Date
KR940010393A true KR940010393A (ko) 1994-05-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930020478A KR940010393A (ko) 1992-10-05 1993-10-05 티타늄 질화물과 폴리실리콘으로 구성되는 적층된 층들을 이용하는 게이트 전극

Country Status (4)

Country Link
EP (1) EP0614226A1 (ko)
JP (1) JPH06342883A (ko)
KR (1) KR940010393A (ko)
TW (1) TW300669U (ko)

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WO2022164286A1 (ko) * 2021-01-29 2022-08-04 삼성전자 주식회사 수신한 데이터 기록의 시간을 동기화하는 전자 장치 및 그 방법

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US6140167A (en) * 1998-08-18 2000-10-31 Advanced Micro Devices, Inc. High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation
US6084280A (en) * 1998-10-15 2000-07-04 Advanced Micro Devices, Inc. Transistor having a metal silicide self-aligned to the gate
US6410967B1 (en) 1998-10-15 2002-06-25 Advanced Micro Devices, Inc. Transistor having enhanced metal silicide and a self-aligned gate electrode
DE19945433C2 (de) * 1999-09-22 2002-03-28 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit Speicher- und Logiktransistoren
WO2001041544A2 (en) * 1999-12-11 2001-06-14 Asm America, Inc. Deposition of gate stacks including silicon germanium layers
EP1183727A1 (en) * 2000-02-17 2002-03-06 Koninklijke Philips Electronics N.V. SEMICONDUCTOR DEVICE WITH AN INTEGRATED CMOS CIRCUIT WITH MOS TRANSISTORS HAVING SILICON-GERMANIUM (Si 1-x?Ge x?) GATE ELECTRODES, AND METHOD OF MANUFACTURING SAME
KR100387259B1 (ko) * 2000-12-29 2003-06-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
SG111968A1 (en) 2001-09-28 2005-06-29 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
JP4736313B2 (ja) 2002-09-10 2011-07-27 日本電気株式会社 薄膜半導体装置
US7316962B2 (en) 2005-01-07 2008-01-08 Infineon Technologies Ag High dielectric constant materials
US20060151845A1 (en) * 2005-01-07 2006-07-13 Shrinivas Govindarajan Method to control interfacial properties for capacitors using a metal flash layer
JP2008016538A (ja) * 2006-07-04 2008-01-24 Renesas Technology Corp Ｍｏｓ構造を有する半導体装置及びその製造方法
US7776680B2 (en) * 2008-01-03 2010-08-17 International Business Machines Corporation Complementary metal oxide semiconductor device with an electroplated metal replacement gate
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022164286A1 (ko) * 2021-01-29 2022-08-04 삼성전자 주식회사 수신한 데이터 기록의 시간을 동기화하는 전자 장치 및 그 방법

Also Published As

Publication number Publication date
TW300669U (en) 1997-03-11
EP0614226A1 (en) 1994-09-07
JPH06342883A (ja) 1994-12-13

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19931005

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid