KR940008661B1 - Data slicer for caption image device - Google Patents

Abstract

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Description

Data Slicer Device of Caption Imaging Device

1 is a block diagram of a conventional data slicer apparatus.

2 is a block diagram of a caption video signal.

(A)-(d) of FIG. 3 are examples of errors by the conventional caption data slicer apparatus.

4 is a block diagram of a data slicer apparatus of the present invention.

(A)-(e) of FIG. 5 is a waveform diagram of each part of the data slicer apparatus of this invention.

* Explanation of symbols for main parts of the drawings

13, 20: shift register 14, 21: latch

15: counter 16, 18: comparison unit

17: addition unit 19: data start determination unit

The present invention relates to a data slicer device of a caption imaging apparatus, which performs data slicer processing accurately using TTl (Transistor Transistor Logic) without using PLL (Phase Locked Loop) or the like for caption data extraction.

In the conventional data slicer, as shown in FIG. 1, a slicer 1 for clamping a 2 Vpp composite video signal to a TTL level of 5 Vpp, a PLL 2 for matching caption data slice timing, and the 5 Vpp A preprocessor (5) for digitally processing the output signal of the slicer (1) clamped by the shunt, a shift register (3) for sampling and storing the output of the preprocessor (5) under the control of the PLL (2), and the shift register (3) It consists of an 8-bit latch 4 that stores the output and provides it to the CPU. Referring to the slice operation of the caption data by the conventional apparatus configured as described above are as follows.

First, the caption video signal is shown on the 21st line of the radix field as shown in FIG. 2, and its structure is 7 cycles of 503 KHz, and a clock (CRI: Clock Run-In) (T3) for synchronizing with data. And a first bit including a start bit (T4) at which a high signal is always output so that a 17-bit NRZ code is encoded at 503 kbps to indicate the start of caption data, and each caption data (D0-D6) T5) and the second byte (T7), and parity bits (T6) (T8) for detecting an error when outputting the respective data (D0-D6), where T1 is a horizontal synchronization signal, T2 is a color burst, and T9 is next. Horizontal sync signal of the line.

Therefore, the conventional slicer apparatus digitally processes the composite image signal (caption line) converted into the TTL level by the slicer 1 by the preprocessor 5 as shown in FIGS. 1 and 2. Since the caption data is encoded at 503kbps (± 5%) when inputting the composite video signal, the 8-bit shift register 3 and the 8-bit latch 4 are operated with a clock of 503KHz to sample at 503KHz. At this time, the phase Clock (P3) phase of the PLL 2 is phase locked to sample the sampling period of the 8-bit shift register 3 in synchronization with the data period. Therefore, when the 8-bit shift register 3 samples one byte (T5) of data (D0-D6), the data is latched to the 8-bit latch (4) with a clock of 503/8 KHz to give the data (D0-D6) to the CPU. To pass. Thereafter, the sampling period of the 8-bit shift register 3 is sampled in synchronization with the data period, thereby extracting the data D0-D6 of the second byte T7 by the same operation as described above. However, in the conventional data slicer apparatus, as shown in (a) of FIG. 3, the data is not synchronized with the sampling period at the time of data extraction, and is sampled at the moment (1 → 0 or 0 → 1) when the data transitions, or (b) of FIG. As shown in (c) of FIG. 3, errors such as sampling of noise such as a glitches due to an inconsistent phase of the CRI (T3) in the PLL (2) as shown in FIG. There was a problem.

The present invention recognizes the start bit of the caption data with simple logic by extracting the data using only the TTL element without using the PLL or the like to solve the conventional problem, and extracts the correct data of the caption data slicer by multiple samplings. When explaining the configuration and effect of the present invention by the accompanying drawings that have the purpose to facilitate as follows.

First, as shown in FIG. 4, the data slicer apparatus of the present invention includes a slicer 11 for clamping a 2Vpp composite video signal to a TTL level of 5VTpp, and a preprocessor for digitally processing the 5Vpp clamped composite video signal. 12), a shift register 13 and a latch 14 for plurally sampling the caption data of the caption line in units of 1 bit, and a counter 15 and a comparator for detecting that plural sampling of each bit is completed during the sampling operation. (16), an adder (17) and a comparator (18) for evaluating whether the corresponding bit value is high or low by evaluating the sampling value of the multisampling completion data detected by the comparator (16), and a caption line A data start determination unit 19 for recognizing the data start bit of the data start signal and outputting a timing control signal of the data slice operation, and capturing the plurality of sampling completion data of each bit as final caption data. Consists of a shift register 20 and the latch 21 to pass the caption data of the line to the CPU, where reference numeral 22 is an AND gate. As shown in FIG. 4, the effect of the present invention configured as described above is 2Vpp synthesized video signal is sliced by the slicer 11, clamped to 5Vpp of TTL level, and digitally processed by the preprocessor 12. The digitally processed composite video signal is data in units of 1 bit by a 3 MHz clock of the AND gate 22 starting at the start bit T4 as shown in FIG. 5A by the 8-bit register 13. Sampling). That is, since one bit data is processed at 503 kbps, six sample values are obtained for each bit using the 3 MHz clock output from the AND gate 22. The sampled output signal is inputted to the adder 17 by the 8-bit latch 4 when the signal L1 is input to the 8-bit latch 14, indicating that the sampling of 1 bit data is completed. Enter it. At this time, after the start bit T4 starts, the 4-bit counter 15 counts the 3 MHz clock output from the AND gate 22, and the 4-bit comparator 16 generates a plurality of data (D0-D6) in units of bits. 6 times) It is determined that sampling is completed.

That is, when the output value of the 4-bit counter 15 becomes "6", a high signal is output to the output terminal A = B of the 4-bit comparator 16, and the six-sampling processing for one bit is completed at this signal output. 8-bit latch 14 latches the sample value six times and count-clears (CLR) the 4-bit counter 15 by the output terminal (A = B) signal of the 4-bit comparator 16. In the bit shift register 20, pulses L1 to L3 used to sample 1 bit data (output of the 4 bit comparator 18) are output.

On the other hand, the adder 17 adds the number of " 1 " of the 6 bits to the 4-bit comparator 18 in the 6-bit sampling value output from the 8-bit latch 14, and inputs the " 1 " Is the number of " 1 " determined by the 4-bit comparison unit 18 to be compared with the reference value P determined for determining that the sampling value of the data D0-D6 is the logic " 1 " If P = 3 times or more, it outputs high (A> B = high), and the rest outputs low (A> B = low), and the caption data that determines whether the caption data is high or low for each bit is 8 Transfer to bit shift register 20. The high and low signals of the 4-bit comparator 18 input to the 8-bit shift register 20 are clocked by the sampling completion signal L3 six times per bit of the 4-bit comparator 16. After sampling 16 bits, when the sampling is completed, the 8-bit latch 21 latches the caption data to the CPU. At this time, when the output signal S1 of the data start determination unit 19 is input to the 8-bit latch 21 by sampling 17 times, the start bead T4 is discarded and only the remaining 16 bits are taken.

On the other hand, the data start determination unit 19, to which the image signal, the caption line signal, and the data start signal are input, recognizes the start bit T4, which indicates the start of the data of the caption signal, and shifts 8 bits from the start bit T4. The output signal S is output to start sampling through the register 13 and the end gate 22. When the sampling is completed after the start bit T4 starts, the data start determination unit 19 receives the latch signal S1. The caption data is output by the 8-bit latch 21 to latch the caption data. That is, as shown in (a) to (e) of FIG. 5, the video signal ((a)), the caption line signal ((b)), and the data start start signal ((c)) are logically multiplied by FIG. As shown in (d), a timing signal starting before the start of the start bit (T4) and ending before the start of the 2-bit data (D0) is detected. Based on this, a high signal is displayed at the start of the caption line as shown in (e). The sampling start signal S output as a low signal is generated by the next synchronization signal T9. During the period where the signal S is high, a 3 MHz clock is supplied to the shift register 13 and the counter 15 through the AND gate 22. Here, the video signal of the caption line is the horizontal synchronization signal T1, the color burst T2, the CRI T3, the start bit T4, the first byte T5, the parity bit T6, and the second byte T7. , A parity bit (T8), and a horizontal synchronization signal (T9) on the next line.

As described above, the caption data is extracted only by the TTL element, and the start of the caption data is recognized by simple logic, and the sampling of the caption data slicer is facilitated by a plurality of sampling.

Claims (1)

A shift register 13 and a latch 14 for plural sampling operations in units of 1 bit by a clock signal having a higher frequency than the data; and a counter for detecting that plural sampling of each bit is completed during sampling or the like. And an adder 17 and a comparer 17 for evaluating a sampling value of the multi-sampling completed data detected by the comparator 16 to determine whether the corresponding bit value is high or low. 18), a data start determining unit 19 for recognizing the data start bit of the caption line and outputting a timing control signal of the data slice operation, and classifying the plurality of sampling completion data of each bit as the final caption data on the caption line. A data slicer device of a caption imaging apparatus comprising a shift register (20) and a latch (21) for transferring caption data to a CPU.