JP2961750B2 - Microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in pulse width determination circuit used in a remote control device (hereinafter, referred to as a remote control) using infrared rays.

[Prior Art] The pulse width of a remote control signal pulse has conventionally been determined as follows.

The remote control signal transmitted by infrared light is converted into an electric signal by an infrared sensor, and then subjected to waveform shaping and input to the microcomputer as a pulse signal having two long and short pulse widths. The microcomputer receives the pulse signal and detects a rising edge and a falling edge by an edge detection circuit. Separately, a counter that counts with a clock of a constant frequency is provided, and a count value when a rising edge is detected is taken into a capture register and then stored in a memory. Next, the count value at the time when the falling edge is detected is taken into the capture register, and this count value is compared with the count value at the rising edge stored in the memory to determine the length of the pulse width of the received pulse. , Judge short. Based on the determination result, the determination values “1” and “0” are stored in the memory in accordance with the length and shortness of the pulse width. Through the same operation, the determination result of the pulse width of the series of pulses is stored in the memory. The above processing is performed by performing a software interrupt when a remote control signal is input to the microcomputer.

[Problem to be Solved by the Invention] Each time the pulse width is measured, the conventional pulse width determination system described above captures a count value as software interrupt processing, stores the captured value in a memory, and By obtaining the capture value, taking the difference from the previous capture value, and comparing this difference with the reference value, the judgment value “1” or “0” is stored in the memory.
There is a drawback that it takes time on software and during that time you cannot work with other software.

[Means for Solving the Problems] A microcomputer according to the present invention has a built-in pulse width determination circuit, and stores a determination value of this determination circuit in a shift register used in a conventional clock synchronous serial interface circuit. It is configured as follows.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a pulse width determination circuit and a shift register according to an embodiment of the present invention. In the figure, ▲ ▼ is a serial clock input terminal,
A pulse signal that has been subjected to pulse width modulation when a remote control signal is received is input to this terminal. The selector 3 accepts the pulse signal and sends the signal to any one of the lines in accordance with the decision as to whether or not to pass the signal through the noise removal circuit 4. The pulse signal is input to the count clock control circuit 13,
Rising edge detection circuit 10 and falling edge detection circuit 5
Is input to The count clock control circuit 13 receives a pulse from the serial clock input terminal and outputs a drive pulse to the shift register 12 having 8 bits. The output of the rising edge detection circuit 10 is input to the reset terminal of the first flip-flop 11, the output of the falling edge detection circuit 5 is input to the clock input terminal of the second flip-flop 2, and the counter 6 And the count value of this counter is cleared to 0. The count 6 counts the output clock of the count clock circuit 7, and the count value is compared with the set value of the comparison register 8 in the comparison circuit 9. The output of the comparison circuit 9 is input to the set terminal of the first flip-flop 11. The output Q1 of the first flip-flop 11 is input to the data input terminal of the second flip-flop 2, and the output Q2 of the second flip-flop 2 is input to the selector 1. The selector 1 is a circuit that selects one of the input signal of the serial-in terminal SI and the output signal of the second flip-flop 2 and inputs the selected signal to the shift register 12. The output of the shift register 12 can be taken out through the serial out terminal SO.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. 2, which is a timing chart of each unit. First, the selector 1 selects the output of the flip-flop 2 and the selector 3 selects the noise removal circuit 4. As shown in FIG. 2, the serial clock input terminal ▲ ▼ receives a pulse having a period 2T (the logical value in this case is “0”) and a pulse having a period 4T (the logical value in this case is “1”). Remote controller signal is input to the noise reduction circuit 4 via the selector 3.
Is input to The noise elimination circuit 4 samples the signal with a constant sampling clock and outputs the level when the level is the same n times or more, and holds the previous level when the level is less than n times. When the falling edge detection circuit 5 detects the falling edge of the remote control signal, it clears the count value of the counter 6. The counter 6 starts counting from 0 newly with the clock supplied from the count clock circuit 7. The comparison register 8 receives an intermediate value 3T between a “2” cycle of “0” value and a 4T cycle of “1” value of the remote control signal. When the cycle until the next falling edge is 2T of “0” value, no match signal is output from the comparison circuit 9. The first flip-flop 11 is reset by the rising edge of the remote control signal output from the rising edge detection circuit 10 and holds its output at 0.

If the cycle until the next falling edge is 4T with a “1” value,
The match signal is output from the comparison circuit 9 and the first flip-flop 11 is set. The flip-flop 11 outputs its output Q1 until the next rising edge signal comes.
It is held at "1" as shown in the figure. The output Q1 of the first flip-flop 11 becomes the input of the second flip-flop 2, and at the falling edge of the remote control signal, the second flip-flop 2 latches this, and as shown in FIG. Output as output Q2. This second flip-flop 2
Is input to the shift register 12 via the selector 1. When receiving the remote control signal, the count clock control circuit 13 drives the shift register 12 by receiving the remote control signal. That is, the output Q2 is latched in the shift register at the rising edge of the remote control signal, and is shifted to the right at each rising edge. In this way, when the remote control signal is 011010 as shown in FIG. 2, the value of the shift register 12 becomes 0011010. The signal is completely converted to digital values "0" and "1". When 8-bit data is input to the shift register, the count clock control circuit 13 issues a control pulse to the CPU and issues an interrupt request.

When the period from the falling edge to the next edge is longer than 4T, the counter 6 outputs the overflow signal OVF.
Is output, and it is determined that the input signal is not a remote control signal.

When this circuit is used as a normal clock synchronous serial interface circuit, the serial clock is input to the serial clock input terminal ▲ ▼, and the serial input signal input to the serial in terminal SI is shifted by the serial clock to the shift register 12. Is output from the serial out terminal SO.

[Effects of the Invention] As described above, the microcomputer according to the present invention can perform all processes from pulse input to determination of pulse width and storage of the determination value in the shift register on hardware without software. Even when the pulse width is being determined, the software work can be freely performed.

When the pulse width is not determined, the circuit can be operated as a clock synchronous serial interface, so that a circuit added for determining the pulse width can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 2 is a timing chart showing signal waveforms at various parts in FIG. 1 ... selector, 2 ... second flip-flop, 3 ...
... selector, 4 ... noise removal circuit, 5 ... falling edge detection circuit, 6 ... counter, 7 ... count clock circuit, 8 ... comparison register, 9 ... comparison circuit, 10 ...
Rising edge detection circuit, 11 first flip-flop, 12 shift register, 13 count clock control circuit, ▲ ▼ serial clock input terminal, SI
…… Serial in terminal, SO …… Serial out terminal.

Claims (1)

(57) [Claims] A serial clock input terminal to which a serial clock or a pulse signal subjected to pulse width modulation is input, a pulse width determination circuit for converting the pulse signal into a digital signal, and a signal from the serial clock input terminal. A count clock control circuit that outputs a clock, a selector that receives a serial input signal and an output of the pulse width determination circuit, selects and outputs any of the signals, and a clock that the count clock control circuit outputs And a shift register for receiving an output signal of the selector.