KR940004274B1 - 이종구조 갈륨 비소 반도체 장치의 소자분리 방법 - Google Patents
이종구조 갈륨 비소 반도체 장치의 소자분리 방법 Download PDFInfo
- Publication number
- KR940004274B1 KR940004274B1 KR1019900021806A KR900021806A KR940004274B1 KR 940004274 B1 KR940004274 B1 KR 940004274B1 KR 1019900021806 A KR1019900021806 A KR 1019900021806A KR 900021806 A KR900021806 A KR 900021806A KR 940004274 B1 KR940004274 B1 KR 940004274B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- gallium arsenide
- forming
- substrate
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (1)
- 서로 상이한 구조를 갖는 적어도 두 개 이상의 소자들이 하나의 동일한 기판상에 형성되는 이종 구조의 갈륨 비소 반도체 장치를 제조하기 위해 상기 적어도 두 개 이상의 소자들 상호간을 전기적으로 분리하는 방법에 있어서, 분자선 에피택시(MBE) 방법을 이용하여 반절연성 갈륨 비소 기판(1)의 표면 위에 제1구조의 소자를 형성하기 위한 제1의 에피층(2)을 형성하는 단계와, 상기 제1에피층(2)의 표면 위에 제1의 알루미늄 갈륨 비소층(3b)과 절연성 갈륨 비소층(3c) 및 제2의 알루미늄 갈륨 비소층(3a)을 순차로 증착하여 절연층(3)을 형성하되 상기 제1 및 상기 제2의 알루미늄 갈륨 비소층(3a, 3b)은 소정의 온도에서 동일한 조건으로 형성하고 상기 갈륨 비소층(3c)은 상기 제1 및 상기 제2의 알루미늄 갈륨 비소층(3a, 3b)의 형성온도보다 상대적으로 낮은 온도에서 형성하는 단계와, 상기 절연층(3)의 상면에 제2의 에피층(4)을 성장시킨 후 상기 제2에피층(4)의 표면에 감광막을 도포하고 마스크를 사용하여 상기 제1구조의 소자가 형성될 영역에 감광막 패턴(5)을 형성하는 단계와, 상기 감광막 패턴(5)을 형성하는 단계와, 상기 감광막 패턴(5)을 마스크로서 사용하여 상기 제2의 알루미늄 갈륨 비소층(3a)과 상기 갈륨 비소층(3c) 및 상기 제1의 알루미늄 갈륨 비소층(3b)을 순차로 식각한 후 상기 감광막 패턴(5)을 제거하여 상기 제1구조 및 상기 제2구조의 소자가 각각 형성될 영역에 제1의 에피층(2)과 제2의 에피층(4a)이 드러나게 하는 단계와, 상기 제1의 에피층(2)의 표면과 상기 제2의 에피층(4a)의 표면 위에 금속막을 소정의 두께로 증착한 후 각 소자의 활성영역에 해당하는 영역에만 금속막이 남도록 금속막 패턴(6)을 형성하는 단계와, 기판의 표면에 소정의 두께로 감광막을 도포한 후 마스크를 사용하여 감광막 패턴(5a)을 형성하는 단계와, 상기 감광막 패턴(5a)을 마스크로서 이용하여 기판에 붕소(B) 이온과 프로톤(H+) 이온을 소정의 에너지로 주입하여 기판에 수직방향으로 소자 분리 영역(7)을 형성하는 단계를 포함하는 것을 특징으로 하는 이종 구조 갈륨 비소 반도체 장치의 소자 분리 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900021806A KR940004274B1 (ko) | 1990-12-26 | 1990-12-26 | 이종구조 갈륨 비소 반도체 장치의 소자분리 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900021806A KR940004274B1 (ko) | 1990-12-26 | 1990-12-26 | 이종구조 갈륨 비소 반도체 장치의 소자분리 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920013671A KR920013671A (ko) | 1992-07-29 |
KR940004274B1 true KR940004274B1 (ko) | 1994-05-19 |
Family
ID=19308467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900021806A Expired - Fee Related KR940004274B1 (ko) | 1990-12-26 | 1990-12-26 | 이종구조 갈륨 비소 반도체 장치의 소자분리 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940004274B1 (ko) |
-
1990
- 1990-12-26 KR KR1019900021806A patent/KR940004274B1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR920013671A (ko) | 1992-07-29 |
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