KR940002743B1 - Pusy d-type latch - Google Patents
Pusy d-type latch Download PDFInfo
- Publication number
- KR940002743B1 KR940002743B1 KR1019910023501A KR910023501A KR940002743B1 KR 940002743 B1 KR940002743 B1 KR 940002743B1 KR 1019910023501 A KR1019910023501 A KR 1019910023501A KR 910023501 A KR910023501 A KR 910023501A KR 940002743 B1 KR940002743 B1 KR 940002743B1
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- South Korea
- Prior art keywords
- nmos
- transistor
- current
- pmos
- current mirror
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- 230000010365 information processing Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 발명의 퍼지 D형 래치 회로도.1 is a fuzzy D-type latch circuit diagram of the present invention.
제2a 내지 d도는 제1도에 따른 출력파형도.2a to d are output waveforms according to FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,3 : 엔모스전류미러 2,4 : 피모스전류미러1,3: NMOS current mirror 2,4: PMOS current mirror
CTL : 제어단자 MN1-MN5: 엔피엔트랜지스터CTL: Control Terminal MN 1 -MN 5 : Enfine Transistor
MP1-MP5: 피엔피트랜지스터MP 1 -MP 5 : PNP transistor
본 발명은 퍼지 D형 래치회로에 관한 것으로, 특히 퍼지논리를 이용한 퍼지정보처리에 적합하도록 한 퍼지 D형 래치회로에 관한 것이다.The present invention relates to a fuzzy D type latch circuit, and more particularly, to a fuzzy D type latch circuit suitable for fuzzy information processing using fuzzy logic.
일반적으로 퍼지정보처리를 수행하기 위해서는 전류레벨의 퍼지논리를 래치시키는 래치회로가 필요하게 된다.In general, in order to perform the fuzzy information processing, a latch circuit for latching the fuzzy logic of the current level is required.
본 발명은 이러한 점을 감안하여 전류레벨의 퍼지논리를 래치시키는 전류모드형 퍼지 D형 래치회로를 창안한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In view of the above, the present invention has been made a current mode fuzzy D-type latch circuit for latching the fuzzy logic of the current level, which will be described in detail with reference to the accompanying drawings.
제1도는 본 발명의 퍼지 D형 래치회로도로서, 이에 도시한 바와 같이 입력신호(IN)를 엔모스트랜지스터(MN1, MN2)로 구성된 엔모스 전류미러(1) 및 피모스트랜지스터(MP1, MP2)로 구성된 피모스전류미러(2)를 통해 엔모스트랜지스터(MN3)의 드레인에 접속하고, 제어단자(CTL)를 상기 엔모스트랜지스터(MN3) 및 피모스트랜지스터(MP5)의 게이트에 접속하고, 상기 엔모트랜지스터(MN3)의 소스를 엔모스트랜지스터(MN4, MN5)로 구성된 엔모스전류미러(3) 및 피모스트랜지스터(MP3, MP4)로 구성된 피모스전류미러(4)를 통해 최조출력단자(IOUT)에 접속하고, 그 접속점을 상기 피모스트랜지스터(MP5)의 소스에 접속하고, 그 피모스트랜지스터(MP5)의 드레인을 상기 엔모스트랜지스터(MN3)와 엔모스전류미러(3)의 접속점에 접속하여 구성한다.FIG. 1 is a fuzzy D-type latch circuit diagram of the present invention, and as shown therein, the input signal IN is composed of the enmos transistors MN 1 and MN 2 and the NMOS current mirror 1 and the PMOS transistor MP 1. , MP 2 ) is connected to the drain of the NMOS transistor MN 3 through a PMOS current mirror 2, and a control terminal CTL is connected to the NMOS transistor MN 3 and the PMOS transistor MP 5 . Is connected to the gate of the NMOS transistor MN 3 and the source of the PMOS comprising an NMOS current mirror 3 composed of NMOS transistors MN 4 and MN 5 and PMOS transistors MP 3 and MP 4 . connected to choejo output terminals (I OUT) via a current mirror (4), and wherein the connection point PMOS connected to the source of the transistor (MP 5), and the PMOS transistor (MP 5), the NMOS transistors to the drain of It is configured by connecting to the connection point of (MN 3 ) and the NMOS current mirror (3).
이와 같이 구성한 본 발명의 작용 및 효과를 상세히 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured as described above in detail.
제1도에 도시한 바와 같이, 제어단자(CTL)에 고전위가 입력되면, 이에 따라 엔모스트랜지스터(MB3)는 턴-온되고, 피모스트랜지스터(MP5)는 턴-오프된다.As shown in FIG. 1, when the high potential is input to the control terminal CTL, the n-MOS transistor MB 3 is turned on and the P-MOS transistor MP 5 is turned off.
이때 입력단자(IN)에 전류 a가 입력되면, 그 전류 a는 엔모스전류미러(1), 피모스전류미러(2), 엔모스트랜지스터(MN3), 엔모스전류미러(3) 및 피모스전류미러(4)를 통해 최종출력단자(IOUT)에서 그대로 출력된다.At this time, when a current a is input to the input terminal IN, the current a is the NMOS current mirror 1, the PMOS current mirror 2, the NMOS transistor MN 3 , the NMOS current mirror 3 and the P Through the MOS current mirror 4, it is output as it is at the final output terminal (I OUT ).
반면, 제어단자(CTL)에 저전위가 입력되면, 이에 따라 엔모스트랜지스터(MN3)는 턴-오프되고, 피모스 트랜지스터(MP5) 턴-온된다.On the other hand, when the low potential is input to the control terminal CT L , the NMOS transistor MN 3 is turned off and the PMOS transistor MP 5 is turned on.
따라서 엔모스트랜지스터(MN3)의 턴-오프로 인해 입력단자(IN)에 입력된 전류 a는 더이상 최종출력단자(IOUT)에 영향을 주지 못하는 반면, 피모스트랜지스터(MP5)가 턴-온됨으로 인해 전상태의 출력전류(Q)가 피모스트랜지스터(MP5)를 통해 엔모스전류미러(3)와 피모스전류미러(4)를 거쳐 최종출력단자(IOUT)로 출력된다.Therefore, the current a inputted to the input terminal IN no longer affects the final output terminal I OUT due to the turn-off of the NMOS transistor MN 3 , whereas the PMOS transistor MP 5 is turned off. Due to the on state, the output current Q of the entire state is output to the final output terminal I OUT through the NMOS current mirror 3 and the PMOS current mirror 4 through the PMOS transistor MP 5 .
이를 제2a도와 같이 나타낼 수 있다.This may be represented as in FIG. 2a.
즉, 제2b도와 같은 제어신호가 제어단자(CTL)에 입력되고, 제2b도와 T1, T2, T3구간에서 a,b' 상승된 b,c' 상승된 c의 전류가 입력단자(IN)로 각기 입력된다고 가정한다면, 제2d도와 같이 T1구간에서 최종출력단자(IOUT)에는 제어신호가 고전위이면 전류 a가 그대로 출력되고, 저전위로 반전되면 전상태의 출력전류(Q), 즉 전류 a가 출력된다.That is, a control signal as shown in FIG. 2b is input to the control terminal CTL, and the current of c raised by b and c 'is increased in the interval between the second b and T 1 , T 2 , and T 3 . Assuming that the input signal is input to IN), the current a is output as it is to the final output terminal I OUT in the T 1 section as shown in FIG. That is, the current a is output.
또한, T2구간에서도 제어신호가 고전위이면 전류 a보다 b'만큼 상승된 전류 b가 그대로 출력되고, 반면에 저전위로 반전되면 전상태의 출력전류(Q)인 전류 b가 출력된다.In addition, in the T 2 section, if the control signal is at high potential, the current b raised by b 'from the current a is output as it is. On the other hand, when inverted to the low potential, the current b, which is the output current Q of the previous state, is output.
또한, 마찬가지로 T3구간에서도 제어신호가 고전위이면 전류 a보다 c'만큼 상승된 전류 c가 그대로 출력되고, 반면에 저전위로 반전되면 전상태의 출력전류(Q)인 전류 C가 출력된다.Similarly, in the T 3 section, if the control signal is at high potential, the current c raised by c 'from the current a is output as it is. On the other hand, when inverted to the low potential, the current C, which is the output current Q of the full state, is output.
이상에서 설명한 바와 같이 본 발명은 전류레벨의 퍼지논리치를 제어신호에 따라 a 또는 전상태의 출력 전류(Q)로, 출력함으로서 퍼지정보처리에 유용한 효과가 있다.As described above, the present invention outputs the fuzzy logic value of the current level as a or the output current Q of the entire state according to the control signal, thereby having a useful effect in the purge information processing.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023501A KR940002743B1 (en) | 1991-12-19 | 1991-12-19 | Pusy d-type latch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023501A KR940002743B1 (en) | 1991-12-19 | 1991-12-19 | Pusy d-type latch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930015327A KR930015327A (en) | 1993-07-24 |
| KR940002743B1 true KR940002743B1 (en) | 1994-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910023501A KR940002743B1 (en) | 1991-12-19 | 1991-12-19 | Pusy d-type latch |
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|---|---|
| KR (1) | KR940002743B1 (en) |
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1991
- 1991-12-19 KR KR1019910023501A patent/KR940002743B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR930015327A (en) | 1993-07-24 |
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