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KR930015327A - Fuzzy D-type latch circuit - Google Patents

Fuzzy D-type latch circuit Download PDF

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Publication number
KR930015327A
KR930015327A KR1019910023501A KR910023501A KR930015327A KR 930015327 A KR930015327 A KR 930015327A KR 1019910023501 A KR1019910023501 A KR 1019910023501A KR 910023501 A KR910023501 A KR 910023501A KR 930015327 A KR930015327 A KR 930015327A
Authority
KR
South Korea
Prior art keywords
current mirror
transistor
nmos
pmos
fuzzy
Prior art date
Application number
KR1019910023501A
Other languages
Korean (ko)
Other versions
KR940002743B1 (en
Inventor
김정범
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910023501A priority Critical patent/KR940002743B1/en
Publication of KR930015327A publication Critical patent/KR930015327A/en
Application granted granted Critical
Publication of KR940002743B1 publication Critical patent/KR940002743B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback

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  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음No content

Description

퍼지 D형 래치회로Fuzzy D-type latch circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 퍼지 D형 래치 회로도.1 is a fuzzy D-type latch circuit diagram of the present invention.

제2a 내지 d도는 제1도에 따른 출력파형도.2a to d are output waveforms according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,3 : 엔모스전류미러 2,4 : 피모스전류미러1,3: NMOS current mirror 2,4: PMOS current mirror

CTL : 제어단자 MN1-MN5: 엔피엔트랜지스터CTL: Control Terminal MN 1 -MN 5 : Enfine Transistor

MP1-MP5: 피엔피트랜지스터MP 1 -MP 5 : PNP transistor

Claims (1)

입력단자(IN)를 엔모스전류미러(1) 및 피모스전류미러(2)를 통해 엔모스트랜지스터(MN3)의 드레인에 접속하고, 제어단자(CTL)를 상기 엔모스트랜지스터(MN3) 및 피모스트랜지스터 (MP5)의 게이트에 접속한 후 상기 엔모스트랜지스터(MN3)의 소스를 엔모스전류미러(3) 및 피모스전류미러(4)를 통해 최종출력단자(IOUT)에 접속하고, 그 접속점을 상기 피모스트랜지스터(MP5)의 소스에 접속하고, 그 피모스트랜지스터(MP5)의 드레인을 상기 엔모스트랜지스터(MN3)와 엔모스전류미러(3)의 접속점에 접속하여 구성된 것을 특징으로 하는 퍼지 D형 래치회로.The input terminal IN is connected to the drain of the NMOS transistor MN 3 through the NMOS current mirror 1 and the PMOS current mirror 2, and the control terminal CTL is connected to the NMOS transistor MN 3 . And the source of the NMOS transistor MN 3 is connected to the gate of the PMOS transistor MP 5 through the NMOS current mirror 3 and the PMOS current mirror 4 to the final output terminal I OUT . connection, and the connection point of the the junction PMOS connected to the source of the transistor (MP 5), and the PMOS transistor (MP 5), the NMOS transistor (MN 3) and the NMOS current mirror (3), the drain of the A fuzzy D type latch circuit characterized in that it is connected and configured. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023501A 1991-12-19 1991-12-19 Pusy d-type latch KR940002743B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023501A KR940002743B1 (en) 1991-12-19 1991-12-19 Pusy d-type latch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910023501A KR940002743B1 (en) 1991-12-19 1991-12-19 Pusy d-type latch

Publications (2)

Publication Number Publication Date
KR930015327A true KR930015327A (en) 1993-07-24
KR940002743B1 KR940002743B1 (en) 1994-03-31

Family

ID=19325232

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910023501A KR940002743B1 (en) 1991-12-19 1991-12-19 Pusy d-type latch

Country Status (1)

Country Link
KR (1) KR940002743B1 (en)

Also Published As

Publication number Publication date
KR940002743B1 (en) 1994-03-31

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