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KR940001160A - Signal processing structure to preselect memory address data - Google Patents

Signal processing structure to preselect memory address data Download PDF

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Publication number
KR940001160A
KR940001160A KR1019920010986A KR920010986A KR940001160A KR 940001160 A KR940001160 A KR 940001160A KR 1019920010986 A KR1019920010986 A KR 1019920010986A KR 920010986 A KR920010986 A KR 920010986A KR 940001160 A KR940001160 A KR 940001160A
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KR
South Korea
Prior art keywords
memory
address
memory address
data
signal processing
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Application number
KR1019920010986A
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Korean (ko)
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KR0153537B1 (en
Inventor
김봉남
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김광호
삼성전자주식회사
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Priority to KR1019920010986A priority Critical patent/KR0153537B1/en
Publication of KR940001160A publication Critical patent/KR940001160A/en
Application granted granted Critical
Publication of KR0153537B1 publication Critical patent/KR0153537B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

본 발명은 메모리를 내장하는 신호 처리 칩에서 메모리의 번지 데이타를 선행 선택하는 신호처리 구조에 관한 것이다. 본 발명에 의한 신호처리 구조는 메모리 번지 콘트롤을 명령어 페치와 독립적으로 수행하여 프로그램 데이타 출력과 동시에 메모리 번지 저장 레지스터에서 해당 메모리 번지를 선택하여 선택된 메모리 번지 레지스터로 전송하고 상기 메모리 번지 레지스터는 메모리 명령어 디코더의 출력신호에 의하여 제어되도록 구성하므로서, 동일한 메모리로서 동작속도의 고속화가 이루어짐으로서 사용자로 하여금 더욱 빨라진 액세스시간을 느끼게 하는 효과가 있게 되고, 또한 향후 메모리의 크기가 커지는 추세에 대비할 수 있게 된다.The present invention relates to a signal processing structure for preselecting the address data of a memory in a signal processing chip incorporating a memory. The signal processing structure according to the present invention performs memory address control independently from instruction fetch, selects the corresponding memory address from the memory address storage register and transfers it to the selected memory address register at the same time as the program data output and the memory address register is a memory instruction decoder. It is configured to be controlled by the output signal of the, because the speed of the operation speed is made as the same memory, the effect is to make the user feel faster access time, and it is possible to prepare for the trend of increasing the size of the memory in the future.

Description

메모리 번지 데이타를 선행 선택하는 신호 처리 구조Signal processing structure to preselect memory address data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 기술에 의한 신호처리 구조에 따른 블럭도.1 is a block diagram according to a signal processing structure according to the prior art.

제2도는 제1도의 리드동작 파형도.2 is a waveform diagram of the read operation of FIG.

제3도는 본 발명에 의한 신호처리 구조에 따른 블럭도.3 is a block diagram according to a signal processing structure according to the present invention.

제4도는 제3도의 리드동작 파형도.4 is a waveform of the read operation of FIG.

Claims (1)

메모리를 내장하는 신호처리 회로에 있어서, 수신되는 프로그램 데이타로부터 페치신호에 동기되는 명령어를 출력하는 명령어레지스터와, 상기 명령어레지스터와 접속되며 상기 명령어를 디코딩하여 메모리 리드 신호 및 메모리 라이트 신호를 발생하는 메모리명령어디코더와, 상기 수신되는 프로그램 데이타로 부터 상기 메모리의 번지를 선택하기 위한 콘트롤 데이타를 출력하는 메모리번지콘트롤러와, 상기 메모리번지콘트롤러와 접속되며 상기 콘트롤 데이타에 의해 상기 메모리의 번지를 선택하기 위한 번지 데이타를 출력하는 메모리번지저장레지스터와, 상기 메모리명령어디코더와 접속되어 상기 메모리 리드 신호 및 메모리 라이트 신호를 수신하며 상기 두 신호를 논리 조합하여 액세스 신호를 발생하는 게이트와, 상기 메모리번지저장레지스터의 출력을 수신하며 상기 게이트의 출력에 의해 상기 번지데이타를 출력하는 메모리번지출력레지스터와, 상기 메모리번지출력레지스터와 접속되며 상기 수신되는 번지 데이타를 디코딩하여 상기 메모리로 출력하는 메모리번지디코더를 구비하여 상기 메모리의 번지 콘트롤을 명령어 페치와 독립적으로 수행함으로서 상기 프로그램 데이타 출력과 동시에 메모리 번지를 선택할 수 있도록 동작함을 특징으로 하는 신호처리장치의 메모리 엑세스 회로.A signal processing circuit incorporating a memory, comprising: an instruction register for outputting an instruction synchronized with a fetch signal from received program data, and a memory connected to the instruction register and decoding the instruction to generate a memory read signal and a memory write signal A command address decoder, a memory address controller for outputting control data for selecting the address of the memory from the received program data, and a address for connecting with the memory address controller and for selecting the address of the memory by the control data A memory address storage register for outputting data, a gate connected to the memory command decoder to receive the memory read signal and a memory write signal, and logically combining the two signals to generate an access signal, and the memory address storage register And a memory address output register for receiving the output of the master and outputting the address data by the output of the gate, and a memory address decoder for decoding the received address data and outputting the address data to the memory. And performing address control of the memory independently of command fetch so that the memory address can be selected simultaneously with the output of the program data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920010986A 1992-06-24 1992-06-24 Signal processing structure to preselect memory address data KR0153537B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920010986A KR0153537B1 (en) 1992-06-24 1992-06-24 Signal processing structure to preselect memory address data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920010986A KR0153537B1 (en) 1992-06-24 1992-06-24 Signal processing structure to preselect memory address data

Publications (2)

Publication Number Publication Date
KR940001160A true KR940001160A (en) 1994-01-10
KR0153537B1 KR0153537B1 (en) 1998-12-01

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Publication number Priority date Publication date Assignee Title
KR20200134183A (en) 2020-11-05 2020-12-01 오경순 Fixed structure of sheet panels for building interior and exterior
KR20220071159A (en) 2022-05-13 2022-05-31 오경순 A method of fixing between a mold and a sheet panel of an exterior panel constructed by an open joint method and an exterior panel manufactured thereby

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