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KR930020987A - Line interpolation signal generator and method using line memory and TTL - Google Patents

Line interpolation signal generator and method using line memory and TTL Download PDF

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Publication number
KR930020987A
KR930020987A KR1019920004827A KR920004827A KR930020987A KR 930020987 A KR930020987 A KR 930020987A KR 1019920004827 A KR1019920004827 A KR 1019920004827A KR 920004827 A KR920004827 A KR 920004827A KR 930020987 A KR930020987 A KR 930020987A
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South Korea
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signal
memory
output
line
converter
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KR1019920004827A
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KR950002657B1 (en
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강권학
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

본 발명은 고화질 TV의 2배속 신호에 요구되는 라인 보간신호 발생장치 및 방법에 관한 것으로써 수입 의존도가 높아 가격상승의 원인이 되었던 원칩(one-chip) IC로 된 보간신호 발생기를 저렴하고 구하기 쉬운 TTL과 메모리를 이용하여 구성하고 원신호와 보간신호를 리드 인에이블 신호에 의해 출력 하였으며 특히 보간신호를 발생하는데 단지 2개의 가산기와 메모리로 된 지연기를 이용하였다.The present invention relates to an apparatus and method for generating line interpolation signals required for double speed signals of high definition TVs. It consists of TTL and memory, and outputs original signal and interpolation signal by read enable signal. Especially, only two adders and memory delayers are used to generate interpolation signal.

이와같은 발명으로 고가의 라인 보간신호 발생기의 수입에서 탈피하여 경제성을 기할 수 있고, 2배속 신호의 선명한 TV영상을 재현할 수 있다.This invention can be economical by avoiding the import of expensive line interpolation signal generator, it is possible to reproduce a clear TV image of the double speed signal.

Description

라인 메모리와 TTL을 이용한 라인 보간신호 발생장치 및 방법Line interpolation signal generator and method using line memory and TTL

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 전체 블럭도.1 is an overall block diagram of the present invention.

제2도는 본 발명의 보간신호 발생부.2 is an interpolation signal generator of the present invention.

Claims (2)

라인 영상신호를 입력으로 하여 디지탈 변환하여 출력하는 A/D변환기(1)와, 상기 A/D변환기(1)로부터 입력된 신호를 지연하여 출력하는 지연부(2)와, 상기 A/D변환기(1)로 부터의 출력과 상기 지연부(2)로부터의 출력을 가수와 피가수로 하여 가산하는 가산부(4)와, 상기 지연부(2)로부터의 출력을 래치하는 래치부(3)와, 상기 가산부(4)로부터의 출력을 일시 저장하는 메모리B(6)와, 상기래치부 (3)의 출력을 일시 저장하는 메모리 A(5)와, 상기 메모리A(5)와 상기 메모리 B(6)의 출력을 제어하는 반전게이트(7)와, 상기 메모리A(5) 또는 상기 메모리B(6)의 디지탈 출력을 아날로그 변환하여 출력하는 D/A변환기(8)로 구성되어지는 것을 특징으로 하는 라인메모리와 TTL을 이용한 라인 보간신호 발생장치.An A / D converter 1 for digitally converting and outputting a line video signal, a delay unit 2 for delaying and outputting a signal input from the A / D converter 1, and the A / D converter An adder (4) for adding the output from (1) and the output from the delay unit (2) as a mantissa and an addee, a latch unit (3) for latching the output from the delay unit (2); Memory B (6) for temporarily storing the output from the adder (4), memory A (5) for temporarily storing the output of the latch unit (3), the memory A (5) and the memory B And an inverting gate 7 for controlling the output of (6), and a D / A converter 8 for converting and outputting the digital output of the memory A 5 or the memory B 6 by analog conversion. Line interpolation signal generator using line memory and TTL. 라인영상신호는 원신호와 보간신호로 구성되는 바, 원신호는 입력된 아날로그신호를 A/D변환부 지연하는 단계와, 상기 지연된 디지탈 신호를 래치하여 일시 저장하는 단계와, 상기 저장된 디지탈 신호를 출력제어신호에 따라 D/A변환하여 출력하는 단계로 이루어지며, 보간신호는 입력된 아날로그신호를 A/D변환하는 단계와, 상기 변환된 디지탈신호와 상기 지연된 디지탈 신호를 가감산하여 보간신호를 발생하는 단계와, 상기 발생된 디지탈 신호를 출력제어신호에 따라 D/A변환하여 출력하는 단계로 구성되어지는 것을 특징으로 하는 라인메모리와 TTL을 이용한 라인 보간신호 발생방법.The line video signal is composed of an original signal and an interpolation signal. The original signal includes delaying an input analog signal by an A / D converter, latching the delayed digital signal, and temporarily storing the delayed digital signal, and storing the stored digital signal. A D / A conversion is performed according to an output control signal, and the interpolation signal is subjected to A / D conversion of an input analog signal, and the interpolation signal is added to or subtracted from the converted digital signal and the delayed digital signal. And generating and converting the generated digital signal by D / A conversion according to an output control signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920004827A 1992-03-25 1992-03-25 Line interpolation signal generator and method using line memory and TTL Expired - Fee Related KR950002657B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920004827A KR950002657B1 (en) 1992-03-25 1992-03-25 Line interpolation signal generator and method using line memory and TTL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920004827A KR950002657B1 (en) 1992-03-25 1992-03-25 Line interpolation signal generator and method using line memory and TTL

Publications (2)

Publication Number Publication Date
KR930020987A true KR930020987A (en) 1993-10-20
KR950002657B1 KR950002657B1 (en) 1995-03-24

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KR950002657B1 (en) 1995-03-24

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