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KR930003430A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR930003430A
KR930003430A KR1019910012538A KR910012538A KR930003430A KR 930003430 A KR930003430 A KR 930003430A KR 1019910012538 A KR1019910012538 A KR 1019910012538A KR 910012538 A KR910012538 A KR 910012538A KR 930003430 A KR930003430 A KR 930003430A
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KR
South Korea
Prior art keywords
oxide film
semiconductor device
gate oxide
polycrystalline silicon
silicon layer
Prior art date
Application number
KR1019910012538A
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Korean (ko)
Other versions
KR950001152B1 (en
Inventor
최영석
유광동
원태영
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019910012538A priority Critical patent/KR950001152B1/en
Publication of KR930003430A publication Critical patent/KR930003430A/en
Application granted granted Critical
Publication of KR950001152B1 publication Critical patent/KR950001152B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음.No content.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명에 따른 반도체장치의 단면도,2 is a sectional view of a semiconductor device according to the present invention,

제3(A)∼(D)도는 이 발명에 따른 반도체장치의 제조공정도이다.3 (A) to (D) are manufacturing process diagrams of the semiconductor device according to the present invention.

Claims (8)

게이트와 드레인이 중첩된 반도체장치에 있어서, 제1도전형의 반도체기판과, 상기 반도체기판내에 형성되어 채널영역에 의해 이격되며 각각이 저농도 및 고농도영역들을 가지는 소오스 및 드레인영역과, 상기 채널영역의 상부에 제2게이트산화막을 개재시켜 형성된 제1다결정실리콘층과, 상기 제2게이트산화막이 형성되어 있지 않은 반도체기판의 상부에 형성된 제1게이트산화막을 개재시켜 상기 저농도영역과 중첩되고 상기 제1다결정실리콘층의 측면과 접촉되는 ‘L’자형의 제2다결정 실리콘층과, 상기 제2다결정 실리콘층의 ‘L’자 내부에 형성된 스페이서를 구비한 반도체장치.A semiconductor device in which gates and drains overlap, a semiconductor substrate of a first conductivity type, a source and drain region formed in the semiconductor substrate and spaced apart by a channel region, each having low concentration and high concentration regions, A first polycrystalline silicon layer formed by interposing a second gate oxide film thereon and a first gate oxide film formed on an upper portion of a semiconductor substrate on which the second gate oxide film is not formed, and overlapping the low concentration region and overlapping the first polycrystal. And a second polycrystalline silicon layer having an 'L' shape in contact with a side surface of the silicon layer, and a spacer formed inside the 'L' shape of the second polycrystalline silicon layer. 제1항에 있어서, 상기 제1게이트산화막이 200∼300Å정도 두께를 가지는 반도체장치.The semiconductor device according to claim 1, wherein said first gate oxide film has a thickness of about 200 to about 300 microseconds. 제1항에 있어서, 상기 제2게이트산화막이 150∼200Å정도 두께를 가지는 반도체장치.The semiconductor device according to claim 1, wherein said second gate oxide film has a thickness of about 150 to 200 microseconds. 제1항에 있어서, 상기 제다결정실리콘층이 500∼800Å정도 두께를 가지는 반도체장치.The semiconductor device according to claim 1, wherein said polycrystalline silicon layer has a thickness of about 500-800 GPa. 게이트와 드레인이 중첩된 반도체장치의 제조방법에 있어서, 제1도전형의 반도체기판 상부에 상기 제1게이트산화막과 질화막을 순차적으로 형성하는 공정과, 상기 반도체기판의 소정부분을 노출하고 재차 상기 제1게이트산화막보다 얇은 제2게이트산화막을 형성하는 공정과, 상술한 구조의 전표면에 상기 제2게이트산화막의 상부에 질화막의 표면보다 더 높게 싸이도록 제1다결정실콘층을 형성하는 공정과, 상기 제2게이트산화막에서 표면이 상기 질화막의 표면과 일치하도록 제1다결정 실리콘층을 제거하고 질화막을 제거하는 공정과, 상기 제1다결정실리콘을 마스크로하여 제2도전형의 저농도 이온 주입 영역을 형성하는 공정과, 상술한 구조의 전표면에 제2다결정실리콘층과 산화막을 형성하는 공정과, 상기 산화막을 에치백하여 스페이서를 형성하는 공정과 상기 스페이서를 마스크로하여 노출된 제2다결정실리콘층을 제거하고 제2도전형의 불순물을 고농도로 이온주입한 후 열처리하여 저농도 및 고농도 영역으로 이루어지는 소오스 및 드레인 영역을 형성하는 공정으로 이루어지는 반도체장치의 제조방법.A method of manufacturing a semiconductor device in which a gate and a drain overlap each other, the method comprising: sequentially forming the first gate oxide film and the nitride film on an upper surface of the first conductive semiconductor substrate, exposing a predetermined portion of the semiconductor substrate, and again forming the first substrate. Forming a second gate oxide film thinner than the one-gate oxide film, forming a first polycrystalline silicon layer on the entire surface of the above structure so as to be wrapped higher than the surface of the nitride film on the second gate oxide film; Removing the first polycrystalline silicon layer and removing the nitride film so that the surface of the second gate oxide film coincides with the surface of the nitride film; and forming a low concentration ion implantation region of the second conductive type using the first polycrystalline silicon as a mask. Forming a second polysilicon layer and an oxide film on the entire surface of the structure described above; and etching the oxide film to form a spacer. Is a process of removing the exposed second polysilicon layer using the spacer as a mask, implanting impurities of the second conductivity type at high concentration, and performing heat treatment to form source and drain regions composed of low concentration and high concentration regions. Method of manufacturing a semiconductor device. 제5항에 있어서, 상기 질화막을 3000∼4000Å정도 두께로 형성하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 5, wherein the nitride film is formed to a thickness of about 3000 to 4000 microns. 제5항에 있어서, 상기 제1다결정실리콘층을 에치백 또는 폴리싱하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 5, wherein the first polycrystalline silicon layer is etched back or polished. 제7항에 있어서, 상기 제1다결정실리콘층을 에치백할 때 질화막을 식각 종료점으로 이용하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 7, wherein a nitride film is used as an etching end point when the first polycrystalline silicon layer is etched back. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910012538A 1991-07-20 1991-07-20 Semiconductor device and manufacturing method thereof KR950001152B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910012538A KR950001152B1 (en) 1991-07-20 1991-07-20 Semiconductor device and manufacturing method thereof

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Application Number Priority Date Filing Date Title
KR1019910012538A KR950001152B1 (en) 1991-07-20 1991-07-20 Semiconductor device and manufacturing method thereof

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KR930003430A true KR930003430A (en) 1993-02-24
KR950001152B1 KR950001152B1 (en) 1995-02-11

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100396895B1 (en) * 2001-08-02 2003-09-02 삼성전자주식회사 Method of fabricating semiconductor device having L-type spacer
KR100448087B1 (en) * 1997-06-30 2004-12-03 삼성전자주식회사 Method for fabricating spacer of transistor to obtain good profile of subsequent interlayer dielectric
KR100469149B1 (en) * 1997-12-31 2005-05-17 주식회사 하이닉스반도체 Manufacturing method of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448087B1 (en) * 1997-06-30 2004-12-03 삼성전자주식회사 Method for fabricating spacer of transistor to obtain good profile of subsequent interlayer dielectric
KR100469149B1 (en) * 1997-12-31 2005-05-17 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100396895B1 (en) * 2001-08-02 2003-09-02 삼성전자주식회사 Method of fabricating semiconductor device having L-type spacer

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