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KR920015619A - Manufacturing method of elevated source / drain MOS FET - Google Patents

Manufacturing method of elevated source / drain MOS FET Download PDF

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Publication number
KR920015619A
KR920015619A KR1019910001091A KR910001091A KR920015619A KR 920015619 A KR920015619 A KR 920015619A KR 1019910001091 A KR1019910001091 A KR 1019910001091A KR 910001091 A KR910001091 A KR 910001091A KR 920015619 A KR920015619 A KR 920015619A
Authority
KR
South Korea
Prior art keywords
film
insulating film
forming
depositing
semiconductor substrate
Prior art date
Application number
KR1019910001091A
Other languages
Korean (ko)
Inventor
오경석
최원택
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910001091A priority Critical patent/KR920015619A/en
Priority to JP3134286A priority patent/JPH04249327A/en
Publication of KR920015619A publication Critical patent/KR920015619A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

엘리베이티드 소스/드레인형 MOS FET의 제조방법Manufacturing method of elevated source / drain MOS FET

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4A도 부터 제41도는 제3도의 MOS FET의 제조공정순서를 도시한 단면도.4A to 41 are sectional views showing the manufacturing process sequence of the MOS FET shown in FIG.

Claims (6)

a) 제1전도형의 반도체기판 상에 엑티브영역을 한정하기 위한 소자분리막을 형성하고 상기 액티브영역상에 박막의 게이트절연막을 형성하는 공정. b) 상기 게이트절연막의 소정영역상에 게이트전극을 형성하기 위해 제1도전막을 침적하고 이어서 상기 제1도전막상에 제1절연막을 침적한 후, 상기 제1절연막 및 제1도전막을 패터닝하여 상기 게이트 전극의 패턴을 형성하는 공정, c) 상기 게이트전극의 패턴 및 상기 소자분리막을 이온주입마스크로 사용하여, 상기 액티브영역에 상기 반도체기판과는 다른 전도형의 불순물을 주입시켜 저농도의 불순물영역을 형성하는 공정, d) 상기 불순물 주입후, 결과물의 전표면에 제2절연막을 균일하게 침적하고 침적된 제2절연막을 이방성식각하여 상기 불순물영역의 표면을 노출시키고 상기 게이트전극의 패턴의 측벽에 스페이서를 형성하는 공정, e) 상기 스페이서 형성후, 결과물의 전표면에 상기 반도체기판과는 다른 전도형의 불순물이 고농도로 도우프된 다결정실리콘막을 침적하고 상기 다결정실리콘막상에 다결정실리콘과 식각선택비가 다른 희생물질층을 상기 소자분리막과 게이트전극의 패턴으로 둘러 싸인 상기 불순물 영역상의 오목한 부분에 채우는 공정, f) 상기 희생물질층 식각마스크로 사용하여 상기 노출된 다결정 실리콘막을 에치백 공정으로 식각하여 상기 불순물영역상에만 다결정 실리콘막을 남기는 공정, g) 상기 다결정실리콘막의 에치백 공정 후, 상기 희생물질층을 완전히 제거하는 공정, 및 h) 상기 제거공정 후, 결과물의 전표면에 제3절연막을 그 표면이 대체적으로 평탄하게 침적하고, 상기 침적된 제3절연막에 콘택홀을 형성하고, 이어서 금속배선을 형성하는 공정을 구비한 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.a) forming a device isolation film for defining an active region on a first conductive semiconductor substrate and forming a gate insulating film of a thin film on the active region; b) depositing a first conductive film to form a gate electrode on a predetermined region of the gate insulating film, and then depositing a first insulating film on the first conductive film, and then patterning the first insulating film and the first conductive film to form a gate electrode. C) forming a pattern of an electrode, c) using a pattern of the gate electrode and the device isolation film as an ion implantation mask to implant impurities of a conductivity type different from that of the semiconductor substrate into the active region to form a low concentration impurity region And d) depositing the second insulating film uniformly on the entire surface of the resultant after implanting the impurity, and anisotropically etching the deposited second insulating film to expose the surface of the impurity region and spacers on the sidewalls of the pattern of the gate electrode. Forming process, e) After forming the spacer, impurities of a conductivity type different from the semiconductor substrate are doped in high concentration on the entire surface of the resultant. Depositing a positive silicon film and filling a sacrificial material layer having a different etching selectivity from the polysilicon layer on the polysilicon film in a concave portion on the impurity region surrounded by a pattern of the device isolation film and the gate electrode, f) the sacrificial material layer etching mask Etching the exposed polycrystalline silicon film using an etchback process to leave a polycrystalline silicon film only on the impurity region, g) removing the sacrificial material layer completely after the etchback process of the polycrystalline silicon film, and h) And after the removing step, depositing a third insulating film on the entire surface of the resultant surface, and forming a contact hole in the deposited third insulating film, and then forming a metal wiring. Method for manufacturing an elevated source / drain MOS FET 제1항에 있어서, 상기희생물질층은 SOG막, BPSG막, LTO막 또는 포토레이지스트막 중 어느 하나인 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.The method of claim 1, wherein the sacrificial material layer is any one of an SOG film, a BPSG film, an LTO film, or a photoresist film. 제1항에 있어서, 상기 제1 및 제2절연막은 CVD산화막인 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.2. The method of claim 1, wherein the first and second insulating films are CVD oxide films. 제1항에 있어서, 제3절연막을 침적한 후, 상기 반도체기판을 급속 고온 열처리하는 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.The method of claim 1, wherein the semiconductor substrate is subjected to a rapid high temperature heat treatment after the third insulating film is deposited. 제1항에 있어서, 상기 제1도전막은 상기 반도체기판과는 다른 전도형의 불순물이 고농도로 도프된 다결정실리콘으로 형성하는 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.The method of claim 1, wherein the first conductive film is formed of polycrystalline silicon doped with a high concentration of impurities of a conductivity type different from that of the semiconductor substrate. 제1항에 있어서, 상기 제1도전막은 불순물이 도프된 다결정실리콘 및 고유엄 실리사이드 복합층으로 된 것을 특징으로 하는 엘리베이티드 소스/드레인형 MOS FET의 제조방법.The method of claim 1, wherein the first conductive layer is made of a polycrystalline silicon and a high-silicon silicide composite layer doped with impurities. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001091A 1991-01-23 1991-01-23 Manufacturing method of elevated source / drain MOS FET KR920015619A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910001091A KR920015619A (en) 1991-01-23 1991-01-23 Manufacturing method of elevated source / drain MOS FET
JP3134286A JPH04249327A (en) 1991-01-23 1991-06-05 Method of manufacturing elevated source/drain type MOSFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001091A KR920015619A (en) 1991-01-23 1991-01-23 Manufacturing method of elevated source / drain MOS FET

Publications (1)

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KR920015619A true KR920015619A (en) 1992-08-27

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KR1019910001091A KR920015619A (en) 1991-01-23 1991-01-23 Manufacturing method of elevated source / drain MOS FET

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142708A (en) * 1993-06-21 1995-06-02 Nec Corp Semiconductor device and its manufacture
US6433397B1 (en) 2000-01-21 2002-08-13 International Business Machines Corporation N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03272147A (en) * 1990-03-22 1991-12-03 Oki Electric Ind Co Ltd Formation of mosfet

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JPH04249327A (en) 1992-09-04

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