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KR920010792A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

Info

Publication number
KR920010792A
KR920010792A KR1019910018793A KR910018793A KR920010792A KR 920010792 A KR920010792 A KR 920010792A KR 1019910018793 A KR1019910018793 A KR 1019910018793A KR 910018793 A KR910018793 A KR 910018793A KR 920010792 A KR920010792 A KR 920010792A
Authority
KR
South Korea
Prior art keywords
chip
semiconductor
heat sink
semiconductor device
semiconductor devices
Prior art date
Application number
KR1019910018793A
Other languages
English (en)
Inventor
미쓰하루 시미즈
도시유끼 무라가미
마사또 다나까
가쓰야 후까세
Original Assignee
이노우에 사다오
신꼬오 덴기 고오교오 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이노우에 사다오, 신꼬오 덴기 고오교오 가부시키가이샤 filed Critical 이노우에 사다오
Publication of KR920010792A publication Critical patent/KR920010792A/ko
Priority to KR2019950018901U priority Critical patent/KR960000149Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 수지봉지형 반도체 장치의 일예를 나타낸 단면도,
제2도 및 제3도는 각각 다른 실시예를 나타낸 단면도.

Claims (2)

  1. 반도체 칩이 패키지내에 봉입된 반도체 장치에 있어서, 상기 반도체 칩의 전크숀패턴이 존재하는 칩면에 반도체 칩의 열팽창계수와 비슷한 열팽창계수를 갖는 소재로 된 히트싱크를 칩코트층을 거쳐서 접합한 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 히트싱크가 패키지의 덮개체를 겸용하는 동시에 히트싱크에 설비한 돌출부가 칩코트층을 거쳐서 반도체 칩의 번크숀패턴이 존재하는 칩면에 접합되어 있는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910018793A 1990-11-30 1991-10-25 반도체 장치 KR920010792A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019950018901U KR960000149Y1 (ko) 1990-11-30 1995-07-27 반도체 장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-340496 1990-11-30
JP2340496A JPH04207061A (ja) 1990-11-30 1990-11-30 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR2019950018901U Division KR960000149Y1 (ko) 1990-11-30 1995-07-27 반도체 장치

Publications (1)

Publication Number Publication Date
KR920010792A true KR920010792A (ko) 1992-06-27

Family

ID=18337526

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018793A KR920010792A (ko) 1990-11-30 1991-10-25 반도체 장치

Country Status (2)

Country Link
JP (1) JPH04207061A (ko)
KR (1) KR920010792A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100673938B1 (ko) * 2000-04-26 2007-01-24 삼성테크윈 주식회사 반도체 패키지 및 이의 제조방법

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
US5369056A (en) 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5705851A (en) * 1995-06-28 1998-01-06 National Semiconductor Corporation Thermal ball lead integrated package
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
FR2788882A1 (fr) * 1999-01-27 2000-07-28 Schlumberger Systems & Service Dispositif a circuits integres, module electronique pour carte a puce utilisant le dispositif et procede de fabrication dudit dispositif
JP2007165836A (ja) * 2005-11-18 2007-06-28 Shinko Electric Ind Co Ltd 半導体装置
JP2012015225A (ja) * 2010-06-30 2012-01-19 Hitachi Ltd 半導体装置
JP6008582B2 (ja) * 2012-05-28 2016-10-19 新光電気工業株式会社 半導体パッケージ、放熱板及びその製造方法
JP7367352B2 (ja) * 2019-06-24 2023-10-24 富士電機株式会社 半導体モジュール、車両、および半導体モジュールの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100673938B1 (ko) * 2000-04-26 2007-01-24 삼성테크윈 주식회사 반도체 패키지 및 이의 제조방법

Also Published As

Publication number Publication date
JPH04207061A (ja) 1992-07-29

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Patent event code: PA01091R01D

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Patent event date: 19911025

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Comment text: Request for Examination of Application

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Patent event date: 19950626

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PC1205 Withdrawal of application forming a basis of a converted application
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