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KR910010875A - 논리회로 - Google Patents

논리회로 Download PDF

Info

Publication number
KR910010875A
KR910010875A KR1019890017064A KR890017064A KR910010875A KR 910010875 A KR910010875 A KR 910010875A KR 1019890017064 A KR1019890017064 A KR 1019890017064A KR 890017064 A KR890017064 A KR 890017064A KR 910010875 A KR910010875 A KR 910010875A
Authority
KR
South Korea
Prior art keywords
low
response
input means
designation
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019890017064A
Other languages
English (en)
Other versions
KR930003257B1 (ko
Inventor
요시에 나까바야시
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910010875A publication Critical patent/KR910010875A/ko
Application granted granted Critical
Publication of KR930003257B1 publication Critical patent/KR930003257B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

내용 없음

Description

논리회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명에 의한 논리회로의 1실시예를 나타내는 회로도.

Claims (1)

  1. 출력단자의 로우 하이를 지정하는 신호에 응답하여 상기 출력단자를 저 저위점 및 고전위점의 어느곳인가 한쪽에 선택적으로 접속하는 것에 의하여 로우 및 하이의 논리출력을 행하는 논리회로이고, 상기 출력단자의 로우 하이를 지정하는 신호를 받는 입력수단과, 제어전극이 상기 입력수단에 작동적으로 결합됨과 동시에 제1및 제2전극이 각각 상기 고전위점 및 상기 출력단자에 접속되어 상기 출력단자의 로우 하이를 지정하는 신호의 하이의 지정에 응답하여 온하고 로우의 지정에 응답하여 오프하는 제1의 트랜지스터와, 제어전극이 상기 입력수단에 작동적으로 결합됨과 동시에 제1및 제2전극이 각각 상기 출력단자 및 상기 전위점에 접속되어 상기 출력단자의 로우 하이를 지정하는 신호의 지정에 응답하여 오프하고 하이의 지정에 응답하여 오프하는 제2의 트랜지스터와 상기 제1의 트랜지스터의 제어전극 및 상기 입력수단에 접속되어 상기 입력수단에 주어지는 상기 출력단자의 로우 하이를 지정하는 신호의 로우의 지정에 응답하여 능동화되어 상기 제1의 트랜지스터의 제어전극에 주어지는 전류를 흡수하는 전류흡수수단과를 구비한 논리회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890017064A 1989-02-13 1989-11-23 논리회로 Expired - Fee Related KR930003257B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3418189 1989-02-13
JP1-34181 1989-02-13

Publications (2)

Publication Number Publication Date
KR910010875A true KR910010875A (ko) 1991-06-29
KR930003257B1 KR930003257B1 (ko) 1993-04-24

Family

ID=12407033

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890017064A Expired - Fee Related KR930003257B1 (ko) 1989-02-13 1989-11-23 논리회로

Country Status (2)

Country Link
JP (1) JPH02290329A (ko)
KR (1) KR930003257B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381929B1 (ko) * 1998-06-03 2004-03-26 주식회사 엘지화학 고분자라텍스를연속적으로과립상으로제조하는공정및장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381929B1 (ko) * 1998-06-03 2004-03-26 주식회사 엘지화학 고분자라텍스를연속적으로과립상으로제조하는공정및장치

Also Published As

Publication number Publication date
KR930003257B1 (ko) 1993-04-24
JPH02290329A (ja) 1990-11-30

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