KR910007180B1 - Sid-wall doped trench copacitor cell using self-aligned contact and a method manufacturing thereof - Google Patents

Abstract

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Description

DRAM cell of SDTSAC structure and its manufacturing method

1 is a cross-sectional view of a DRAM cell of an SDTSAC structure fabricated in accordance with the present invention.

2 to 7 is a partial cross-sectional view illustrating in detail the self-aligned contact process method of the main process of the present invention.

* Explanation of symbols for main parts of the drawings

1: P-type substrate 2: Protective layer

3: metal layer 4: third insulating layer

5: poly3 layer for bit line 6: second insulating layer

7: Interconnection poly layer

8 and 8 ': poly2 layer for gate electrode and gate electrode line

9: field oxide film 10: gate oxide film

11 and 11 ': source and drain N + regions

12 dielectric film 13 poly1 layer for charge storage electrode

14: P + diffusion layer for external electrode 15: P-Well area

16 nitride layer 17 first insulating layer

18 and 18 ': oxide film layer

19: Lightly-Doped Drain Area

20: Spacer

The present invention relates to a DRAM (Dynamic Random Access Memory) cell having a Side-Wall Doped Trench Capacitor Cell Using Self-Aligned Contact (SDTSAC) structure of a semiconductor highly integrated memory device, and a method of manufacturing the same. In particular, a drain of a trench capacitor and a mobile gate is disclosed. The present invention relates to a method for fabricating a DRAM cell having an SDTSAC structure capable of minimizing the area of a DRAM cell by forming a connection with and a mobile gate source and a bit line connection through a self-aligned contact process.

DRAM cells having a conventional SDT structure (see patent application 9189 on July 22, 1988) use contact masks to connect a source and a bit line of a moving gate or a drain to a trench capacitor charge storage electrode. . That is, when the gate electrode is formed by using a gate mask to form the gate electrode, and when the contact mask is used to fold the source and bit lines of the moving gate or connect the train and trench capacitor charge storage electrodes, To prevent leakage currents between neighboring interconnect structures, a minimum distance must be provided, and the minimum distance must be set in consideration of misalignment tolerance due to misalignment of the mask. Therefore, the DRAM cell structure made of the above-mentioned SDT structure is so large that it is unsuitable for high-density memory devices of 16 megabytes or more.

Accordingly, the present invention provides a magnet that does not use a contact mask in a process of connecting a bit line to a source of a moving gate and a charge storage electrode of a drain and a trench capacitor to reduce an area of a DRAM cell having a conventional SDT structure. It is an object of the present invention to provide a DRAM cell having a SDTSAC structure and a method of manufacturing the same, which can reduce the area of the DRAM cell by the alignment contact process, thereby reducing the area of the DRAM cell.

According to the structure of the present invention, a trench capacitor is formed inside the silicon substrate and a moving gate is formed on the surface of the neighboring silicon substrate, and the drain N + region of the moving gate is connected by the trench capacitor charge storage electrode and the conductive layer, A DRAM cell in which a source N + region is connected to a bit line conductive layer, wherein the drain N + region is an upper portion of an insulating layer adjacent to a gate electrode and an upper surface of a gate electrode line adjacent to an internal connection poly layer interconnected with a capacitor charge storage electrode. And an inner connection poly layer connected to the source N + region overlapping with a predetermined upper portion of an insulating layer of an upper surface of a neighboring gate electrode, and a predetermined portion of an inner connection poly layer connected to the source N + region. Is characterized in that the bit line is connected to the structure.

According to the manufacturing method of the present invention, a process of forming a P + diffusion region for an external electrode selectively along a trench wall formed by removing a predetermined portion of a P-type substrate, forming a capacitor oxide film on the trench wall and forming a capacitor charge storage electrode on the capacitor oxide film Forming a trench capacitor, depositing a gate oxide film on the adjacent P-type substrate and the field oxide film of the trench capacitor, and then attaching a poly2 layer for gate electrode, a first insulating layer, and a nitride film in a pattern process. Forming a predetermined gate electrode and a gate electrode line, and forming an insulating layer over the gate electrode and the gate electrode line and over the exposed structure, and then forming a spacer on the sidewalls of the gate electrode and the gate electrode line with an anisotropic oxide etch. Charge storage electrode of drain region and trench capacitor Exposing the side surface, removing the nitride film on the gate electrode and the gate electrode line, and then depositing an internal connection poly layer on the exposed whole structure and removing the predetermined internal connection poly layer on the upper portion of the center of the gate electrode and the gate electrode line. Forming a source and a drain N + region by diffusing the high concentration N-type impurities contained in the internal connection poly layer to a P-type substrate by a heat-treating process, and a second insulating layer on the exposed structure. And forming a contact hole in a predetermined portion of the second heat transfer layer on the internal connection poly layer connected to the source, and depositing a bit line conductive layer to connect to the source.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

1 is a cross-sectional view of a DRAM cell having an SDTSAC structure in which a predetermined bit line cell arrangement is arranged in a predetermined portion of a P-type substrate 1 having a P-well region 15 according to the present invention. As shown, a trench is formed to the inside of the P-type substrate 1, and for example, a BSG material (not shown) is deposited on the trench surface, and a photoresist is filled thereon, so that the upper surface of the P-type substrate 1 is formed. After flattening, the photoresist having a predetermined thickness is etched back, the exposed BSG material is removed, the remaining photoresist is completely removed, and then heat-treated to the P-type substrate 1 on the inner wall of the trench by an optional side doping method. An external electrode P + diffusion region 14 is formed (wherein the P-type substrate 1 does not have to have the P-well region 15) and the capacitor dielectric film 12 (for example, on the trench wall surface) Oxide-nitride-oxide) is deposited along the trench surface, and A field oxide film in which the polyl layer 13 for charge storage electrodes is filled to the upper surface of the P-type substrate 1 in the trench in which the body film 12 is deposited, and the device is separated by a LOCOS (Local Oxidation of Silicon) process method. (9) is formed up to a predetermined upper surface of the poly1 layer for charge storage electrode 13 to form a trench capacitor structure.

In addition, a moving gate is formed in a predetermined portion of the P-type substrate 1 adjacent to the trench capacitor, and the drain N + region 11 ′ of the moving gate and the poly1 layer 13 for the capacitor charge storage electrode are formed by a self-aligned contact process method. Interconnected by the interconnecting polylayer 7, and forming interconnecting polylayer 7 on the source N + region 11, on top of which the second heat transfer layer 6, for example LTO (Low) Temperature Oxide layer is formed, and the bit line poly 3 layer 5 is connected to the internal connection poly 1 layer 7 on the top of the source N + region 11 and the third insulating layer 4 is placed on the top. For example, an oxide film layer of BPSG is formed, and a metal layer 3 is formed on the upper surface of the third insulating layer 4, which is coincident with the poly2 layer 8 and 8 'for the gate electrode and the gate electrode line, and the protective layer 2 ) Is formed.

The reason why the metal layer 3 is formed is that when the gate electrode and the gate electrode lines 8 and 8 'are formed long, the resistance is increased and the operation speed of the device is slowed. Each time, the metal layer 3 was connected to the gate electrodes and the gate electrode lines 8 and 8 'to decelerate the resistance.

Meanwhile, the method of manufacturing the moving gate of FIG. 1 and connecting the child gate drain and source N + regions 11 and 11 'with the bit line and the poly1 layer 13 for the charge storage electrode, respectively, are performed by a self-aligned contact process. Since the most important point of the present invention will be described in more detail with reference to FIGS.

FIG. 2 shows the deposition of the gate oxide film 10 on the upper surface of the P-well region 15 of the P-type substrate 1 adjacent to the trench capacitor, and the poly2 layer 8 and the first insulating layer 17 for the gate electrode. And a nitride film 16 is sequentially deposited, and then a sectional view of a pattern process of the gate electrode is formed. The nitride film 16 protects the first insulating layer 17 during the gate electrode pattern process and prevents the oxide film from growing above the first insulating layer 17 during the oxidation process. It should be noted that the gate electrode lines are simultaneously formed on the field oxide film when the gate electrode is formed.

FIG. 3 shows P-to prevent the leakage current between the internal connection poly2 layer 5 formed later on the left and right sides of the gate electrode and the gate electrode, and to reduce the junction depth of the LDD region 19 to be formed later. After the oxide layer 18 is grown on the well region 15 and the left and right side walls of the gate electrode, the LDD region 19 is formed by ion implantation of low concentration N-type impurities.

4 shows the spacer oxide film as a whole on the structure of FIG. 3, and then forms the spacer 20 on the sidewall of the gate electrode with an anisotropic oxide etch. This spacer protects the high concentration N-type impurities of the internal connection poly layer 7 to be formed later into the LDD region 19.

On the other hand, in the case of CMOS fabrication, when the P-MOSFET is simultaneously made with the N-MOSFET, in order to protect the high concentration of N-type impurities contained in the internal connection poly layer 7 in the LDD region of the P-MOSFET, In contrast, the thin oxide layer 18 'is grown on top of the N-well 15' by reference.

FIG. 6 shows that after the process of FIG. 4, the nitride layer 16 is removed on the gate electrode, and the internal connection poly layer 7 is deposited on the exposed area. 7) and the rest are removed, but the internal connection poly layer 7 is formed to overlap the first electrode layer 17 on the gate electrode and the gate electrode line (not shown).

For reference, when the process step of FIG. 4 is performed, the charge storage electrode (not shown) of the trench capacitor and the upper surface of the LDD region may be exposed without performing a separate contact mask process, thereby forming a self-aligned contact.

FIG. 7 shows the source and drain N + regions 11 and 11 'formed by diffusing the high concentration N-type impurities contained in the internal connection poly layer 7 of FIG. 6 into the P-well region 15 by a heat treatment process. Form the second insulating layer 6 as a whole, remove the second insulating layer 6 on the upper part of the internal connection poly layer 7 connected to the source, and deposit the bit line poly 3 layer 5 to connect to the source. Then, a bit line is formed by a pattern process. Here, even when the contact hole is formed to connect the bit line to the source, the self-aligned contact is applied because the area of the contact hole overlaps the poly-layer gate electrode for internal connection even though the area of the contact hole slightly overlaps with the gate electrode.

As described above, in the present invention, after the gate electrode is formed, the process of depositing the internal connection poly layer 7 and the source and drain N + regions 11 and 11 'are formed, and the second insulating layer 6 is deposited. Thereafter, the process of depositing the poly3 layer 5 for the bit line is formed by a self-aligned contact process.

The operation of the present invention is a unit DRAM cell in which a transistor and a capacitor are connected in series, and the source terminal is connected to the bit line and the drain terminal in series with the charge storage electrode of the capacitor to accumulate or erase charges in the capacitor.

According to the present invention, an error due to mask misalignment generated in the mask process for connecting the drain and the charge storage electrode and the mask process for connecting the bit line to the source can be eliminated in the related art. In other words, the size of the DRAM cell in the bit line direction can be reduced to X (error) between the bit line and the gate electrode, 2X between the connection of the drain and the charge storage electrode and the neighboring gate electrode, thus 3X. If the cell size is Y, the DRMA cell area of 3XY can be reduced.

Therefore, in a DRMA cell made of a conventional SDT, for example, X (error) = 0.5 μm and Y = 2.8 μm (depending on the equipment), the area of the cell due to mask misalignment is 3 × 0.5 μm × 2.8 In the present invention, since the cell area (4.2 μm 2) due to the mask misalignment can be reduced in the present invention, it can contribute to high integration of the semiconductor device.

Claims (2)

A trench capacitor is formed inside the silicon substrate, and a moving gate is formed on the surface of the neighboring silicon substrate, and the drain N + region of the moving gate is interconnected by the trench capacitor charge storage electrode and the conductive layer, and the source N + region of the movable gate is bit. A DRAM cell configured to be connected to a line conductive layer, wherein the conductive layer in which the drain N + region is interconnected with a capacitor charge storage electrode is for internal connection so as to overlap a predetermined upper portion of the first insulating layer on the upper surface of the gate electrode line and the neighboring gate electrode. An inner connection poly layer formed of a poly layer and overlapping a predetermined upper portion of the first insulating layer of the upper surface of the adjacent gate electrode, and formed at the center of the inner connection poly layer connected to the source N + region. Capacities made of SDTSAC structure, characterized in that the bit line is connected in a predetermined portion Cell. Forming a P + diffusion region for the external electrode selectively along the trench wall formed by removing a predetermined portion of the P-type substrate, forming a capacitor oxide film on the trench wall, and forming a capacitor charge storage electrode on the capacitor oxide film to form a trench capacitor A process for forming an NMOS transfer gate over the P-type substrate adjacent to the trench capacitor, interconnecting a drain N + region of the transfer gate and a capacitor charge storage electrode, and a source N + of the transfer gate. A DRAM cell manufacturing method comprising a step of connecting a conductive layer for a bit line to a region, wherein after the step of forming the trench capacitor, a gate oxide film is deposited on an adjacent P-type substrate and a field oxide film on the trench capacitor, and is formed thereon. The poly2 layer for the gate electrode, the first insulating layer and the nitride film are deposited in this order. Forming a predetermined gate electrode and a gate electrode line by a gate electrode pattern process; forming an oxide film on the gate electrode and the gate electrode line and on an exposed structure, and then forming spacers on the gate electrode and the sidewall of the gate electrode with an anisotropic oxide etch. At the same time, exposing a predetermined source and drain region and an upper surface of the charge storage electrode of the trench capacitor, removing the nitride film on the gate electrode and the gate electrode line, and then depositing an interconnect poly layer on the exposed whole structure and Separating the poly layer for connection from the upper portion of the center of the gate electrode and the gate electrode line to leave the upper portion of the predetermined source region, drain region and exposed charge storage electrode, and the heat treatment process to remove the high concentration N-type impurities contained in the internal connection poly layer Source and Drain N + by Diffusion to P-type Substrate And forming a second insulating layer as a whole on the exposed structure, and then forming a contact hole in a predetermined portion of the second insulating layer on the internal connection poly layer connected to the source and forming a bit line conductive layer. A DRAM manufacturing method having an SDTSAC structure, comprising depositing and connecting to a source.

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