KR910005317B1 - Interface circuit - Google Patents

Abstract

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Description

Integrated circuit of signaling data, voice data and user data

1 is a block diagram of transmission and reception data.

2 is a, b is a circuit diagram according to the present invention.

3 is an operational waveform diagram according to the present invention.

4 is one embodiment of a general time compression method.

* Explanation of symbols for main parts of the drawings

10: inverter 15: flip-flop

20, 30, 45: Andgate 25: Divider

35: Latch 40: Selective Multiplex

50, 55: serial and parallel register 60: NAND gate

65,70,75: Parallel Serial Registers

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time compression transmission circuit in a two-wire digital telephone. In particular, the present invention provides signaling data, voice data, and user data that can be integrated and transmitted by signaling data, voice data, and user data. It relates to an integrated circuit.

In general, there are three methods for two-wire delivery.

First, frequency division multiplying (FDM), second, echo canceler method (ECM), and third, time compression multiplexing (TCM).

Among them, the time compression method which is inexpensive and easy to integrate is applied in the present invention.

In addition, the time compression method applied in the present invention will be briefly described. When the master (for example, private exchange) after a predetermined transmission relay time T transmits (Tx) as shown in FIG. 4A, the method of FIG. As the slave receives (Rx), the slave transmits (Tx) and the master (Rx) as shown in Figure 4a (Rx) is called a ping pong (ping pong) transmission.

That is, this method compresses the information to be sent per unit time in time, transmits it within a shorter time than the unit time, and allocates the remaining time to the counterpart to transmit the usage information at this time.

In the related art, it is possible to transmit only voice data when using an analog telephone, and thus there is a problem in that a satisfactory service cannot be provided to a user.

Therefore, an object of the present invention is to integrate the signaling data, voice data (voice) and user data (data) using a time compression method to provide a higher quality service to the user signaling data, voice data, users To provide a data integrated circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a data structure of a frame as a data structure for transmitting and receiving between a master (for example, private exchange) and a slave (for example, digital telephone).

As shown in the figure, one frame has a total length of 24 bits.

The first synchronization signal SY1 is data for synchronization and is always # 1. The second synchronization signal SY has frame periods of (1, 0, 0, 0) and represents frame division data.

In addition, the first signaling data SG1 and the second signaling data SG2 are software control signals as communication data between the master and the slave microprocessors, and the data are allocated one bit each.

In addition, voice data of a digital telephone is converted into a digital signal, and voice data loaded as data and user data output from the data terminal are allocated 8 bits each.

Therefore, the first synchronization signal SY1, the second synchronization signal SY2, the first signaling data sg1, and the second signaling data SG2 each have one bit of voice data, and the user data of eight bits. It consists of a total of 24 bits of 4 bits not used.

In addition, a data structure when only a data telephone is used, that is, when using a digital telephone in parallel with a pair of telephone lines, user data can be configured as voice data.

2 is a signaling integrated circuit according to the present invention, an inverter 10 for generating a predetermined first clock signal by inverting an enable signal RXSHEN of a predetermined master clock generator through an input terminal 11; A flip-flop 15 for latching a second synchronization signal SY2 of a predetermined master clock generator through the input terminal 1 in response to the first clock signal of the inverter 10 being input to the clock terminal CK; An AND gate 20 which inputs a transmission enable signal of a predetermined master clock generator through the second synchronization signal SY2 input terminal 11 output from the flip-flop 15 to generate a predetermined clear signal, and The second clock signal of the predetermined master clock generator through the input terminal 2, that is, the 8K clock signal, is divided into two divisions and three divisions as the clock terminal CK is input to generate a 4K division signal and a 2K division signal. Divider 25 to be cleared in accordance with clear signal of 20 And an AND gate 30 for outputting a newly generated second synchronous signal through the output terminal 93 by comparing the 4K divided signal and the 2K divided signal of the divider 25 with the output terminal 93, and the write clock terminal 4. The latch 35 for latching predetermined data through the data bus 3 and the signaling data through the latch 35 as the write clock of the predetermined CPU through the clock terminal CK are inputted. Selective multiplexing 40 selectively latches the 4K divided signal and the 2K divided signal of the divider 25 to generate predetermined first signaling data and second signaling data and output them through the output terminals 94 and 95, respectively. And the third clock signal of the predetermined master clock generator through the input terminal 86, that is, the 8K clock signal and the fourth clock signal of the predetermined master clock generator through the input terminal 87, that is, the 128K clock signal, are compared with both terminals. And gate 45 for generating a predetermined fifth clock signal, and When the fifth clock signal of the AND gate 45 is inputted to the clock terminal CK, a serial / parallel register for serially inputting 8 bits of voice data of a predetermined master through the voice data input terminal 85 and converting them in parallel. 8 and the user data 8 bits of the predetermined master through the data input terminal 88 as inputted to the sixth clock signal of the predetermined master clock generator through the input terminal 89, that is, the 6KHZ clock signal and the clock terminal CK. Is inputted in parallel and converted in parallel to a parallel register 55, a transmit enable signal of a predetermined master clock generator through the input terminal 90, and a seventh clock signal of the predetermined master clock generator through the input terminal 91. That is, the NAND gate 60 generates a predetermined eighth clock signal by comparing the 512 KHZ clock signal with both terminals, and the eighth clock signal of the NAND gate 60 enters the clock terminal CK. Via terminal 92 A 5V signal, i.e., a first synchronization signal, the first signaling data and the second signaling data through the output terminals 93 and 94, respectively, and the upper four bits of the voice data of the serial / parallel register 50 in parallel. A parallel serial register 65 for inputting and serially transmitting through an output terminal 80 as the transmit enable signal of a predetermined master clock generator through the transmit enable terminal 90 is input, and the NAND gate 60. As the predetermined eighth clock signal is input to the clock terminal CK, the lower four bits of the serial and parallel registers 50 and the upper four bits of the serial and parallel registers 55 are input in parallel, respectively, and the clock generator of the predetermined master is input. A parallel serial register 70 which is serially output through the parallel serial register 65 and the output terminal 80 as a transmit enable signal of a predetermined master clock generator is input from the transmitter enable terminal 90 , The nand As the clock signal of the gate 60 is input to the clock terminal CK, the lower 4 bits of the serial and parallel registers 55 input the lower 4 bits of the ground level in parallel to each other through the transmit enable terminal 90. According to the transmit enable signal of a predetermined master clock generator, the parallel serial registers 70 and 65 are configured in series with the output terminal 80.

3A is an operation waveform diagram according to FIG. 1, (a) is a waveform of a frequency synchronization signal generated from a clock generator of a predetermined master, and (b) is a reception enable of a predetermined master clock generator through an input terminal 11; A waveform of the signal RXSHEN, (c) is a waveform of the enable signal TXEN of the predetermined master clock generator through the input terminal 90, and (d) the output terminal Q of the flip-flop 15. (E) is a clear signal waveform outputted from the AND gate 20, and (f) is a waveform of the second clock signal of the predetermined master clock generator through the input terminal 2, that is, the 8K clock signal. (G) is the waveform of the first divided signal through the divider 25, that is, the 4K clock signal, (h) is the waveform of the second divided signal through the divider 25, that is, the 2K clock signal, and (i ) Is the waveform of the second synchronization signal SY2 (T) through the AND gate 30, and (j and k) are the first signaling through the output terminals Q1 and Q2 of the multiplexer 40. Data and second signaling data SG1 (T) and SG2 (T).

3b is an operation waveform diagram according to FIG. 2b, (a) is a waveform of a frequency synchronization signal generated from a predetermined clock generator, and (b) is a fourth clock signal of a predetermined master clock generator through an input terminal 87. FIG. That is, 128KHZ clock waveform, (c) is the sixth clock signal of the predetermined master clock generator through the input terminal 89, that is, 64KHZ clock waveform, (d) is the waveform of the fifth clock signal of the AND gate 45, (X) is a voice data (VOICE) waveform of a predetermined master through the voice data input terminal 85, (b) is a user data (DATA) waveform of a predetermined master through the user data input terminal 85, (s) ) Is the transmit enable signal (TXEN) waveform of the predetermined master clock generator through the input terminal 90, () is the waveform of the eighth clock signal of the NAND gate 60, () is the output terminal (80). ) Is the waveform of transmission data (TXFRAME) through (), and (t) is the waveform of the predetermined clock generator. It is a waveform of 3 clock signals, that is, 8KHZ clock.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1, 2, and 3 described above.

First, all signals cited in the following description are output in synchronization with the frame synchronizing signal of a predetermined master clock generator as shown in FIGS. 3A and 3B.

When the receive enable signal RXSHEN as shown in (b) of FIG. 3a is input from the clock generator of the predetermined master to the inverter 10 through the input terminal 11, the inverter 10 inverts the predetermined first clock. Generate a signal.

As the first clock signal of the inverter 10 is inputted to the clock terminal CK of the flip-flop 15, the period of (1,0,0,0) of the predetermined master is changed as shown in (d) of FIG. 3a. The signal, that is, the second synchronization signal SY2, is latched to the input terminal D of the flip-flop 15.

At this time, the flip-flop 15 inputs the latched signal to one terminal of the AND gate 20 through the output terminal Q as shown in FIG. 3A (d), and the AND gate 20 is input to the other terminal. The receive enable signal RXSHEN is input through the terminal 11.

Therefore, the AND gate 20 generates a predetermined clear signal as shown in (e) of FIG. 3A.

On the other hand, the predetermined second clock signal through the input terminal 2 from the clock generator of the predetermined master, that is, the 8K clock signal as shown in FIG. 3A (f), is input to the divider 25.

The divider 25 divides the first divided signal generated by the predetermined division of the input 8K clock signal, the second divided signal, that is, the 4K divided signal such as (g) and (h) of FIG. 3a and 2K divided signal. The signals are input to both terminals of the gate 30 and simultaneously to the selection input terminals I9 and I10 of the selection multiplex 40.

Here, the divider 25 is cleared every four cycles because the divider 25 is cleared as the clear signal of the AND gate 20 is input to the clear terminal C.

On the other hand, the AND gate 30 generates a second synchronization signal SY2 for comparing and transmitting the first divided signal and the second divided signal of the divider 25.

On the other hand, the latch 35 latches the signaling data of the predetermined central processing unit 8 bits by 8 bits through the data bus 3 so that the write clock signal DTLOCK of the predetermined central processing unit is input. As input through (4), it is input to the input terminal I3 of the multiplexer 40.

The multiplexer 40 bundles the signaling data bit by bit as shown in (j) of FIG. 3a according to the first divided signal and the second divided signal through the divider 25 to generate the first signaling data SG1. The second signaling data SG2 is output through the output lines 94 and 95, respectively.

Meanwhile, the AND gate 45 may include the third clock signal of the predetermined master clock generator as shown in FIG. 3B through the input terminal 86, that is, the 8K clock signal and the diagram 3B through the input terminal 87. As the fourth clock signal of the predetermined master clock generator, that is, the 128K clock signal is input to both terminals, the fifth clock signal as shown in (d) of FIG. 3b is generated and input to the clock terminal CK of the serial / parallel register 50. do.

The serial / parallel register 50 inputs 8 bits of voice data through the input terminal 85 as the fifth clock signal of the AND gate 45 is input to the clock terminal CK. -I8).

In addition, the serial / parallel register 55 of the predetermined master through the input terminal 88 is input as the sixth clock signal of the predetermined master clock generator through the input terminal 89, that is, the 64KHZ clock signal is input to the clock terminal CK. Input user data (data) as input terminal (I1-I8).

At this time, the NAND gate 60 transmits the transmit enable signal TXEN of the predetermined master clock generator as shown in FIG. 3B through the input terminal 90 and the seventh clock of the predetermined master clock generator through the input terminal 91. A signal, i.e., a 512KHZ clock signal, is input to both terminals to generate a predetermined eighth clock signal as shown in FIG. 3B.

In addition, the parallel-to-serial converter 65 receives the 5V signal through the input terminal 92, that is, the first synchronous signal SY1 and the input terminal 93 as the eighth clock signal of the NAND gate 60 is input. The first signaling data SG1 through the second synchronization signal SY2 input terminal 94 and the second signaling data SG2 through the input terminal 95 are respectively input to the input terminals I5-I8. The upper four bits of the voice data through the output terminals O1-O4 of the parallel register 50 are input.

In addition, the parallel serial register 70 receives voice data through the output terminals O5-O8 of the serial / parallel register 50 as the eighth clock signal of the NAND gate 60 is input to the clock terminal CK. Input the lower 4 bits of < RTI ID = 0.0 >) < / RTI > and input the upper 4 bits of the usage data (data) through the output terminals O1-O4 of the serial / parallel register 55.

The parallel register 75 inputs the lower 4 bits of user data through the output terminals O5-O8 of the serial / parallel register 55 to the input terminals I1-I4 and inputs 4 bits of the ground level. Input to terminals I5-I8.

In this case, the parallel serial registers 65, 70, and 75 are sequentially inputted with the first and second synchronous signals as shown in FIG. 1 as the transmit enable signal TXEN through the input terminal 90 is input. (SY1, SY2), first and second signaling data (SG1, SG2), 8 bits of voice data, 8 bits of user data, and 4 null bits that are not used through the output terminal 80. Outputs to a predetermined slave system in series.

As described above, the present invention integrates and transfers the signaling data, voice data, and user data using a time compression method, thereby providing a higher quality service to the user.

Claims (1)

In a transmission circuit for transmitting voice data and user data of a master, an inverted enable signal RXSHEN generated from a clock generator of a predetermined master through an input terminal 11 is inverted. Inverter 10 generating a predetermined first clock signal, and the second synchronization of the predetermined master clock generator through the input terminal 2 as the first clock signal of the inverter 10 is input to the clock terminal (CK) The flip-flop 15 latching the signal and the second synchronous signal of the flip-flop 15 and the transmit enable signal of the predetermined master clock generator through the input terminal 11 are compared with each other to obtain a clear signal at every predetermined period. The AND gate 20 to generate and the predetermined clock signal of the predetermined master clock generator through the input terminal 2 are divided into predetermined signals to generate the first divided signal and the second divided signal. Clearscene of the endgate 20 The output line 93 after newly generating a divider 25 to be cleared according to the present invention, a predetermined second synchronous signal for comparing and transmitting the first divided signal and the second divided signal of the divider 25. Signaling of the predetermined CPU through the data bus 3 as the AND gate 30 and the write clock of the predetermined CPU through the light clock terminal 4 are inputted to the clock terminal CK. The latch 35 for latching data to the input terminals D1-D9, and the output terminals Q1-Q8 of the latch 35 according to the first division signal and the second division signal of the divider 25. A multiplexer 40 for outputting predetermined first signaling data generated by selectively latching signaling data through the output line 94 and outputting second signaling data through the output line 95; A third clock signal of the predetermined master clock generator through 86 and a predetermined master clock through the input terminal 87; The AND gate 45 for generating a predetermined fifth clock signal by comparing the fourth clock signal of the generator with both terminals, and the fifth clock signal of the AND gate 45 is inputted to the clock terminal CK. A serial / parallel register 50 for serially inputting and converting voice data of a predetermined master through the data input terminal 85 and a sixth clock signal of the predetermined master clock generator through the input terminal 89 are clock terminals ( CK) inputs and outputs a serial / parallel register 55 for serially inputting user data of a predetermined master through the data input terminal 88 and converting it in parallel; and a transmission input of the predetermined master clock generator through the input terminal 90. The NAND gate 60 generates a predetermined eighth clock signal by comparing the seventh signal of the master clock generator through the enable signal and the input terminal 91 to both terminals, and the NAND gate 60 of the NAND gate 60. 8th clock signal Input to the clock terminal CK, the first synchronous signal through the input terminal 92, the second synchronous signal through the input terminal 93, the first signaling data through the input terminal 94, the input terminal ( The second signaling data through 95) and the predetermined upper bits of the input voice data of the serial / parallel register 50, respectively, in parallel, and the transmit enable signal of the predetermined master clock generator through the transmit enable terminal 90; Parallel serial register (65) transmitted in series through the output terminal (80) as input, and the eighth parallel signal (50) as the eighth clock signal of the NAND gate (60) is input to the clock terminal (CK). A parallel low-order bit of the serial parallel register 55 and a predetermined high-order bit of the serial parallel register 55 are respectively inputted in parallel and the transmit enable signal of the predetermined master clock generator is transmitted through the transmit enable terminal 90. 65) and the output terminal (80) As a parallel serial register 70 outputs in series and the clock signal of the NAND gate 60 is input to the clock terminal CK, the predetermined low bit and the bit of the ground level of the serial parallel register 55 are respectively input. A parallel output through the parallel registers 70 and 65 and the output terminal 80 as the transmit enable signal of a predetermined master clock generator is input in parallel and inputted through the transmit enable terminal 90. Signaling data, voice data, user data integrated circuit comprising a serial register (75).

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