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KR900702571A - 반도체 장치 및 반도체 기억장치 - Google Patents

반도체 장치 및 반도체 기억장치

Info

Publication number
KR900702571A
KR900702571A KR1019900700018A KR900700018A KR900702571A KR 900702571 A KR900702571 A KR 900702571A KR 1019900700018 A KR1019900700018 A KR 1019900700018A KR 900700018 A KR900700018 A KR 900700018A KR 900702571 A KR900702571 A KR 900702571A
Authority
KR
South Korea
Prior art keywords
insulating film
conductor layer
semiconductor
polycrystalline silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019900700018A
Other languages
English (en)
Other versions
KR940001252B1 (ko
Inventor
마사까즈 기무라
Original Assignee
원본미기재
세이꼬 엡슨 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63111032A external-priority patent/JPH01281761A/ja
Priority claimed from JP63115231A external-priority patent/JPH01283953A/ja
Priority claimed from JP63265303A external-priority patent/JPH0831533B2/ja
Priority claimed from JP63309128A external-priority patent/JPH02155266A/ja
Priority claimed from JP63309127A external-priority patent/JP2800206B2/ja
Application filed by 원본미기재, 세이꼬 엡슨 가부시끼가이샤 filed Critical 원본미기재
Publication of KR900702571A publication Critical patent/KR900702571A/ko
Application granted granted Critical
Publication of KR940001252B1 publication Critical patent/KR940001252B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 장치 및 반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체 장치의 한 실시예를 도시하는 주요 단면도, 제3A도 내지 제3D도는 제1도에 도시하는 본 발명의 반도체 장치의 제조 공정마다의 주요 단면도, 제4D도 및 제4B도는 각각 본 발명의 반도체 기억 장치의 한 실시예를 도시하는 주요 평면도 및 그 B-B 단면도.

Claims (9)

  1. 반도체 기판위에 형성된 제1절연막과, 상기 제1 절연막위에 형성되고, 정전위에 접속된 도체층과, 상기 도체층 위에 형성된 제2절연막과, 상기 제2절연막위에 형성되고, 배선으로서의 저항 영역 및 저항체로서의 고저항 영역의 2영역을 갖는 다결정 또는 단결정의 실리콘막을 갖는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 도체층은 알루미늄, 다결정 실리콘, MO, Ti, W 등의 고융점 금속 또는 상기 고융점 금속의 실리사이드 중의 1개 또는 2개 이상의 물질로 구성이 되어 있는 것을 특징으로 하는 반도체 장치.
  3. 제1항 또는 제2항에 있어서 상기 도체층은 접지되어 있는 것을 특징으로 하는 반도체 장치.
  4. 반도체 기판위에 형성된 제1절연막과, 상기 제1절연막 위에 형성되고, 배선으로서의 저저항 영역 및 저항체로서의 고저항 영역의 2영역을 갖는 다결정 또는 단결정의 실리콘막과, 상기 실리콘막 위에 형성된 제2절연막과 상기 제2절연막 위에 형성되고, 정전압에 접속된 도체층을 갖는 것을 특징으로 하는 반도체 장치.
  5. 고저항의 다결정 실리콘 저항이 배선층에 접속되어 있는 고저항 다결정 실리콘 부하형 메모리 셀을 갖는 반도체 기억 장치에 있어서, 상기 고저항의 다결정 실리콘 저항의 상방 또는 하방의 어느 한편, 혹은 상방 및 하방의 양편으로 각각 절연막을 거쳐서 형성되고, 또한 정전위에 접속된 도체층을 갖는 것을 특징으로 하는 반도체 기억 장치.
  6. 제5항에 있어서, 도체층은 알루미늄, 다결정 실리콘, MO, Ti, W 등의 고융점 금석 또는 상기 고융점 금석의 실리사이드 중의 1개 또는 2개 이상의 물질로 구성이 되어 있는 것을 특징으로 하는 반도체 장치.
  7. 제5항 또는 제6항에 있어서 상기 도체층은 접지되어 있는 것을 특징으로 하는 반도체 장치.
  8. 제5항, 제6항 또는 제7항에 있어서 상기 도체층은 상기 고저항 다결정 실리콘 부하형 메로리 셀의 접지선도 겸하는 것을 특징으로 하는 반도체 장치.
  9. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900700018A 1988-05-07 1989-04-25 반도체 기억장치 Expired - Fee Related KR940001252B1 (ko)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
JP63111032A JPH01281761A (ja) 1988-05-07 1988-05-07 半導体装置
JP111032 1988-05-07
JP63115231A JPH01283953A (ja) 1988-05-11 1988-05-11 半導体装置
JP115231 1988-05-11
JP265303 1988-10-21
JP63265303A JPH0831533B2 (ja) 1988-10-21 1988-10-21 半導体記憶装置
JP63309128A JPH02155266A (ja) 1988-12-07 1988-12-07 半導体記憶装置
JP63309127A JP2800206B2 (ja) 1988-12-07 1988-12-07 半導体記憶装置
JP309128 1988-12-07
JP309127 1988-12-07
PCT/JP1989/000433 WO1989011162A1 (fr) 1988-05-07 1989-04-25 Dispositif a semi-conducteurs et memoire a semi-conducteurs

Publications (2)

Publication Number Publication Date
KR900702571A true KR900702571A (ko) 1990-12-07
KR940001252B1 KR940001252B1 (ko) 1994-02-18

Family

ID=27526471

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900700018A Expired - Fee Related KR940001252B1 (ko) 1988-05-07 1989-04-25 반도체 기억장치

Country Status (4)

Country Link
EP (1) EP0365690B1 (ko)
KR (1) KR940001252B1 (ko)
DE (1) DE68929121T2 (ko)
WO (1) WO1989011162A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479891B1 (ko) * 2001-07-31 2005-03-30 미쓰비시덴키 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210429A (en) * 1990-06-29 1993-05-11 Sharp Kabushiki Kaisha Static RAM cell with conductive straps formed integrally with thin film transistor gates
EP0465170B1 (en) * 1990-06-29 1997-01-08 Sharp Kabushiki Kaisha Static RAM cell
EP0510370B1 (en) * 1991-03-27 1999-08-25 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
US5128738A (en) * 1991-05-16 1992-07-07 At&T Bell Laboratories Integrated circuit
TW222347B (en) * 1992-11-24 1994-04-11 American Telephone & Telegraph SRAM cell with balanced load resistors

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087979B1 (en) * 1982-03-03 1989-09-06 Fujitsu Limited A semiconductor memory device
DE3569172D1 (en) * 1984-08-23 1989-05-03 Toshiba Kk Semiconductor memory device having a polycrystalline silicon layer
US4679171A (en) * 1985-02-07 1987-07-07 Visic, Inc. MOS/CMOS memory cell
JPS62112362A (ja) * 1985-11-11 1987-05-23 Toshiba Corp 半導体メモリのメモリセル構造
JPS62169472A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 半導体集積回路装置
JPH07112014B2 (ja) * 1986-07-09 1995-11-29 株式会社日立製作所 半導体記憶装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479891B1 (ko) * 2001-07-31 2005-03-30 미쓰비시덴키 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
KR940001252B1 (ko) 1994-02-18
HK1014613A1 (en) 1999-09-30
DE68929121T2 (de) 2000-04-20
DE68929121D1 (de) 2000-01-27
EP0365690A4 (en) 1991-11-27
EP0365690B1 (en) 1999-12-22
EP0365690A1 (en) 1990-05-02
WO1989011162A1 (fr) 1989-11-16

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