KR900007676B1 - Circuit for retiming digital data and pulses automatically - Google Patents

Abstract

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Description

Digital automatic phase adjustment retiming circuit

1 is a block diagram of a digital automatic phase adjustment retiming circuit of the present invention based on an input data phase.

2 is a block diagram showing one embodiment of a phase detector and a retiming apparatus of the present invention.

3 is a timing waveform diagram of the main part of FIG. 2 when the phase of the input data is located between the clock and the inverted transition of the inversion clock.

4 is a timing waveform diagram of the main part of FIG. 2 when the phase of the input data is located between the inverted clock and the ascending transition of the clock.

5 is a block diagram showing another embodiment of the phase detector and the retimer of the present invention.

FIG. 6 is a timing waveform diagram of the main part of FIG. 5 when the phase of the input data is located between the clock and the inverted transition of the inversion clock.

FIG. 7 is a timing waveform diagram of the main part of FIG. 5 when the phase of the input data coincides between the inverted clock and the ascending transition of the clock.

8 is a block diagram illustrating one embodiment of a loop processor of the present invention.

9 is a block diagram showing another embodiment of the sequential digital filter of the present invention.

10 is a block diagram showing one embodiment of the phase shifter of the present invention.

11 is a block diagram of a digital automatic phase adjustment retiming circuit of the present invention based on an input clock phase.

* Explanation of symbols for main parts of the drawings

1,12 phase detector and retiming machine 2,13 loop processor

3,14: phase shifter 4: half-cycle delay circuit

5a, 5b: N divider 6: M divider

7: sequential digital filter 8: up / down counter and encoder

9: Up / Down Counter 10: Preset Controller to N

11: m: 1 multiplier FF _{1 to} FF ₈ : D flip-flop

OR _{1 to} OR ₆ : logical OR gate EXOR _{1 to} EXOR ₄ : exclusive OR gate

△ ₁ to △ _m : delay function gate

According to the present invention, when a relative phase difference between data and clock is uncertain or changes with time in a digital data transmission system, data retiming is performed by placing a significant instant of the clock in the eye pattern of the input data. The present invention relates to a digital automatic phase adjustment retiming circuit that prevents errors and increases input jitter tolerance by tracking relative phase changes of clock and data.

When retiming input data with a clock extracted by a resonator, SAW filter, or phase-locked loop (PLL) used as a self-timed clock extraction circuit in a PCM (Pulse Code Modulation) data transmission repeater When re-timing input data into an input clock in an exchange system and a subscriber system of cross-connector elements, or when inputting data and clock in most measuring equipment, the clock and data are different from each other. It has independent phase and detects the phase difference between clock and data having this independent phase and locates the significant moment of the clock at the center of input data to prevent retiming error. An autophase retiming circuit is required that tracks phase changes to increase jitter tolerance. It is.

The jitter tolerance is defined as the maximum jitter value of input data that does not cause an error when retiming the original input data with the clock extracted by applying input data with phase fluctuations to the timing clock regeneration circuit.

Conventional self-regulated timing clock regeneration circuits have a function of extracting a clock from input data and adjusting the position of the retiming clock at the center of the input data by incorporating a voltage-controlled oscillator in itself. There is a problem that the voltage controlled oscillator cannot be used if necessary with a retiming function instead of an extraction function. Although an automatic phase control circuit using digital control has been announced, a configuration other than a part of the phase detector has not been announced and several Since the phase detector is configured using the delay element, the realization is complicated and the significant moment of the clock cannot be located at the eye center.

The present invention has been made to solve the above problems, and an object thereof is to provide a digital automatic phase adjustment retiming circuit used to correctly retime data when a clock is given from the outside.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

) 및 이 클럭에 의해 리타이밍된(Retimed) 데이타(OD), (

)를 출력하는 역활을 행하고, 상기 루프처리기(2)는 상기 위상검출기 및 리타이밍기(1)로 부터 입력된 위상상태 신호(UC),(DC)를 이용하여 데이타와 클럭신호 사이의 위상차를 올바로 조절하도록 리타이밍 클럭의 위상을 제어하는 위상 제어신호(PCS)를 발생시키며 이 제어신호를 상기 위상이동기(3)에 인가시키는 역활을 행하고, 상기 위상이동기(3)는 상기 루프처리기(2)의 제어신호에 따라 입력클럭의 위상을 적절히 조절한 리타이밍 클럭(IC)을 상기 위상검출기 및 리타이밍기(1)로 출력하는 역활을 행하며, 이와같은 구성은 아날로그 위상동기루프(A-PLL)의 구성과 대응되는 디지탈 위상동기루프(D-PLL)의 구성으로 간주할 수 있다.1 shows a digital automatic phase adjustment retiming circuit of the present invention, which is composed of a phase detector and a retiming apparatus 1, a loop processor 2, and a phase shifter 3, and the phase detector and retiming apparatus 1. ) Detects the phase difference between the retiming clock IC and the input data ID from the phase shifter 3, indicating that the phase of the input data is ahead or behind the clock. ) Is applied to the loop processor 2, and the retiming clock OC correctly corrected by the phase shifter 3,

) And Retimed data (OD) by this clock, (

), And the loop processor (2) uses the phase state signals (UC) and (DC) input from the phase detector and the retimer 1 to calculate the phase difference between the data and the clock signal. It generates a phase control signal (PCS) for controlling the phase of the retiming clock to properly adjust and applies this control signal to the phase shifter (3), wherein the phase shifter (3) is the loop processor (2). It outputs the retiming clock (IC) to the phase detector and the retiming device (1) in which the phase of the input clock is properly adjusted according to the control signal of the circuit. The configuration is analog phase synchronization loop (A-PLL). It can be regarded as the configuration of the digital phase locked loop (D-PLL) corresponding to the configuration of.

, OC,

)을 갖고 있으며, 상기 입력단(ID)은 논리합게이트(OR₁)에 입력되게 연결하고 상기 논리합게이트(OR₁)의 한 출력(ID-1)은 D형 플립플롭(FF₁)의 데이타 입력단(D)과 배타적논리합게이트(EXOR₁)의 한 입력단에 연결하며, 상기 논리합게이트(OR₁)의 나머지 한 출력(ID-2)은 D형 플립플롭(FF₂)의 데이타 입력단(D)과 배타적논리합게이트(EXOR₂)의 한 입력단에 연결한다.2 shows an embodiment of the phase detector and retiming apparatus 1 of the present invention, in which two input stages (ID), (IC) and six output stages (UC, DC, OD,

, OC,

), Which has the input terminal (ID) is a logical OR gate (OR ₁₎ to be connected to input and data input terminals of the output (ID-1) is a D-type flip-flop (FF ₁₎ of the OR gate (OR ₁₎ to ( D) and an exclusive logical sum gate (EXOR ₁ ), and the other output (ID-2) of the logic sum gate (OR ₁ ) is exclusive to the data input stage (D) of the D flip-flop (FF ₂ ). Connect to one input of the logic sum gate (EXOR ₂ ).

)은 상기 플립플롭(FF₁)의 클럭입력단에 연결하고, 상기 논리합게이트(OR₂)의 나머지 한출력(OC)은 상기 플립플롭(FF₂)의 클럭입력단에 연결하며, 상기 플립플롭(FF₁)의 출력(S_2-1)은 상기 배타적논리합게이트(EXOR₁)의 나머지 한 입력단에 연결하고 상기 플립플롭(FF₂)의 출력(OD)은 상기 배타적논리합게이트(EXOR₂)의 나머지 한 입력단에 연결한다.Input stage (IC) according to the phase from the mobile device (3) is connected in input to the OR gate (OR ₂₎ and the output of the OR gate (OR ₂₎ (

) Is connected to the clock input terminal of the flip-flop (FF ₁ ), the other output OC of the logic sum gate (OR ₂ ) is connected to the clock input terminal of the flip-flop (FF ₂ ), the flip-flop (FF) ₁₎ the output (S _2-1) is a remainder of the output (OD) is the exclusive-OR gate (EXOR ₂₎ connected to the rest of the input stage and the flip-flop (FF ₂₎ of the exclusive-OR gate (EXOR ₁₎ of Connect to the input.

)은 데이타 입력단(D)에 귀환 연결하고 상기 플립플롭(FF₃)의 출력(

)은 데이타 입력단(D)에 귀환 연결한다.The output (S _2-2) of said exclusive OR gate (EXOR ₁₎ and are commonly connected to the reset input terminal (R) of the D flip-flop clock input terminal and D-type flip-flop (FF ₄₎ of (FF _3), the output (S _2-3) is the flip-flop (FF ₄₎ commonly connected to the reset input terminal (R) of the clock input terminal and the flip-flop (FF ₃₎ and the flip-flop of the exclusive OR gate (EXOR ₂₎ Output of (FF ₃ ) (

) Is connected to the data input terminal (D) feedback and output of the flip-flop (FF ₃ )

) Is fed back to the data input (D).

Remaining output (DC) of the other output (UC) and the flip-flop (FF ₄₎ of the flip-flop (FF ₃₎ is applied to an output signal to the loop processor (2).

)의 오름천이 사이에 위치할 경우 제3도에 도시한 파형과 함께 동작을 설명하면 다음과 같다.In the phase detector and the retiming apparatus 1 having the above-described configuration, first, the phase of the input data, that is, the instant of transition of the input data, is the ascending transition of the clock OC and the inverted clock (

If the upstream of the) is located between the operation described with the waveform shown in Figure 3 as follows.

)에 의해 동작하는 플립플롭(FF₁)에 의해 리타이밍한 데이타(SD-1)를 배타적 논리합게이트(EXOR₁)에 인가하면 상기 배타적 논리합게이트(EXOR₁)의 출력시호(S_2-2)는 입력데이타(ID)의 천이시각과 반전클럭(

)의 오름천이 시각 사이의 시간동안만 "0"이 되고, 또한 입력데이타(ID)와 클럭(OC)에 의해 동작하는 플립플롭(FF₂)에 의해 D 리타이밍한 데이타(OD)를 배타적논리합게이트(EXOR₂)에 인가하면 상기 배타적논리합게이트(EXOR₂)의 출력신호(S_2-3)는 입력데이타(ID)의 천이시각과 클럭(OC)의 오름천이 시각 사이의 시간동안만 "0"이 된다.Whenever data transition occurs at the input (ID), the input data and the inverted clock (

When the data SD-1 retimed by the flip-flop FF ₁ operated by the sigma is applied to the exclusive logic sum gate EXOR ₁ , the output signal S _2-2 of the exclusive logic sum gate EXOR ₁ is applied. Is the transition time of the input data (ID) and the inversion clock (

Exclusive logical sum of D retiming data (OD) by flip-flop (FF ₂ ) operated by input data (ID) and clock (OC). gate (EXOR ₂₎ is applied only for a time between when the exclusive-OR gate (EXOR ₂₎ the output signal (S _2-3) transition is a rise time of the input data (ID) and the transition time clock (OC) of the "0 "Becomes.

)의 오름천이 사이에 있음을 나타내는 업클럭(UC)을 발생한다.Therefore, the output UC of the flip-flop FF ₃ becomes "1" at the moment when the output signal S _2-2 transitions from "0" to "1", and then the output signal S _2-3 becomes As soon as it transitions from "0" to "1", it shifts to "0" so that the phase of the input data ID shifts the clock OC and the inverted clock (

Generates an upclock (UC) indicating that the upstream transition is between.

)의 오름천이와 클럭(OC)의 오름천이 사이에 위치할 경우, 또는 이와 반대인 경우에도 상기 동작과 같은 원리에 의해 동작하며 이 경우는 다운 클럭(DC)신호만이 활성화되고 이때의 파형도를 제4도에 도시하였다.At this time, the flip-flop FF ₄ has a value of "0" because the clock input signal IC is inserted in the state where the input signal S _2-2 to the minute input terminal R is "1" and is not operated by the clock. It stays as it is and the phase of the input data (ID)

In the case of the rising transition of) and the rising edge of the clock (OC), or vice versa, it operates according to the same principle as the above operation, in which case only the down clock (DC) signal is activated and the waveform at this time Is shown in FIG.

, OC,

)를 갖는 회로이다.5 shows another embodiment of the phase detector and the retiming apparatus 1, with two input stages (ID, IC) and six output stages (UC, DC, OD,

, OC,

Is a circuit with

The input stage (ID) is connected in input to the OR gate (OR ₃₎ and connected to the data input terminal (D) of the logical sum output (ID-3) of the gate (OR ₃₎ is (FF _5).

)은 상기 플립플롭(FF₅)의 클럭입력단에 연결하며, 상기 논리합 게이트(OR₄)의 나머지 한 출력(OC)은 D형 플립플롭(FF₆)의 클럭입력단에 연결한다.The input terminal IC is connected to be input to the OR gate OR ₄ , and an output of an OR gate OR ₄ is applied to the input terminal IC.

) Is connected to the clock input of the flip-flop FF ₅ , and the other output OC of the OR gate OR ₄ is connected to the clock input of the D-type flip-flop FF ₆ .

)은 상기 배타적 논리합 게이트(EXOR₃)의 나머지 입력단에 연결하고, 상기 플립플롭(FF₆)의 나머지 한 출력(OD)은 상기 배타적 논리합 게이트(EXOR₄)의 나머지 한 입력단에 연결한다.The output (S _5-1) is the output of flip-flop coupled to one input terminal of exclusive-OR gate (EXOR ₃₎ of the (S _5-2), and the flip-flop (FF ₅₎ of the half-period delay circuit 4 ( FF ₆ is connected to one input of the data input terminal D and the exclusive OR gate EXOR ₄ , and one output of the flip-flop FF ₆ .

) Is connected to the other input terminal of the exclusive OR gate EXOR ₃ , and the other output OD of the flip-flop FF ₆ is connected to the other input terminal of the exclusive OR gate EXOR ₄ .

)은 데이타 입력단(D)에 귀환 연결하고 상기 플립플롭(FF₈)의 출력(

)은 자체데이타 입력단(D)에 귀환 연결한다.The output (S _5-3) of said exclusive OR gate (EXOR ₃₎ and are commonly connected to the reset input terminal (R) of the clock input terminal and D-type flip-flop (FF ₈₎ of the D flip-flop (FF _7), the output (S _5-4) of said exclusive OR gate (EXOR _4), and is commonly connected to the reset input terminal (R) of the clock input, and the flip-flop (FF ₇₎ of said flip-flop (FF _8), the flip- Output of flop (FF ₇ )

) Is connected to the data input terminal (D) feedback and the output of the flip-flop (FF ₈ ) (

) Feedback to its own data input (D).

The remaining outputs (UC) of the other output (DC) and the flip-flop (FF ₈₎ of said flip-flop (FF ₇₎ is applied to an output signal to the loop processor (2).

)의 오름천이 사이에 위치할 경우 제6도에 도시된 파형도에서 알 수 있듯이 입력데이타(ID)의 천이 발생시 입력데이타(ID)의 위상에 관계없이 상기 배타적 논리합 게이트(EXOR₄)의 출력(S_5-4)은 일정한 펄스폭의 구형파를 만드는 반면에 상기 배타적 논리합 게이트(EXOR₃)의 출력(S_5-3)은 입력데이타(ID)의 위상, 즉 반주기 지연회로(4)에 의해 반주기 지연된 입력데이타(ID)의 위상에 의존하는 펄스폭의 구형파를 만든다.In the above configuration, first, the phase of the input data ID shifts the clock OC and the inverted clock (

If the ascending stream is located between, the output of the exclusive OR gate EXOR ₄ when the transition of the input data ID occurs, as shown in the waveform diagram of FIG. 6, regardless of the phase of the input data ID. S _5-4 ) produces a square wave having a constant pulse width, while the output S _5-3 of the exclusive OR gate EXOR ₃ is half-period by the phase of the input data ID, that is, the half-period delay circuit 4. Create a square wave of pulse width that depends on the phase of the delayed input data (ID).

)의 오름천이 사이에 있음을 나타내는 업클럭(UC)을 루프처리기(2)에 인가한다.In addition, since the descending transition times of the two output signals S _5-3 and S _5-4 coincide with each other, the output UC of the flip-flop FF ₈ is equal to the signal S _5-4 at " 0 ". When the transition to "1" is made to "1" and the reset input signal (S _5-3 ) transitions from "0" to "1", the transition to "0" by the transition of the input data (ID) Phase shift of clock (OC) and inversion clock (

The upclock UC is applied to the loop processor 2, indicating that the upstream transition of N is between.

In this case, the flip-flop FF ₇ does not operate by a clock because the clock input signal S _5-3 is inserted into the reset terminal R while the clock input signal S _5-4 is “1”. It stays as "0".

)의 오름천이와 클럭(OC)의 오름천이 사이에 위치할 경우 또는 이와 반대인 경우에도 상기 동작과 같은 원리에 의해 동작하며 이 경우는 다운클럭(DC) 신호만이 활성화 되고 이때의 파형도를 제7도에 도시하였다.Phase of input data ID is inverted clock

In the case of rising between the rising edge of the clock and the rising edge of the clock (OC) or vice versa, it operates according to the same principle as the above operation, in which case only the down clock (DC) signal is activated and the waveform diagram at this time is 7 is shown.

The loop processor (2) is used to obtain an effective operation against the change of the input data phase due to the interference between the input data and the pulse. The simple hardware that performs this function is the digital phase synchronous loop (D-PLL) field. The instantaneous digital filter used in the present invention is shown in FIG. 8, and the loop processor 2 is composed of a sequential digital filter 7, an up / down counter and an encoder 8, and the sequential digital filter 7 ) Is applied to the up clock (UC) and the down clock (DC), when the count value exceeds N by the respective N dividers (5a), (5b), respectively, the up control signal (UCON) and the down control signal (DCON) ) Is applied to the up / down counter and encoder (8).

In addition, the up clock UC and the down clock DC are applied to the OR gate OR ₅ to divide in the M divider 6, and when the divided value exceeds M, all dividers 5a and 5b. , (6) to reset.

Here, if any of the two N division counters 5a and 5b exceeds the N coefficient value, and the M division counter 6 exceeds M, the N division counters 5a and 5b are reset to be up-controlled. The signal UCON and the down control signal DCON remain unchanged. This function prevents the up control signal UCON and the down control signal DCON from being affected by the unwanted signal.

9 shows another embodiment of the sequential digital filter 7 in the loop processor 2, where the initial state of the up / down counter 9, which can count from ψ to 2N, is set to N and then the upclock (UC). And when the up / down counter 9 is set to N by the preset controller 10 to N when the down clock DC reaches ψ or 2N, the up control signal UCON or the down control signal ( DCON) and its operation performance is similar to that shown in FIG.

Phase synchronization (3) for phase control signal (PCS) for proper phase control when up control signal (UCON) or down control signal (DCON) is input by using the up / down counter and encoder (8) as an address address controller. M: 1 is output to the multiplexer (11).

There are many kinds of phase shifters 3 and one embodiment of the present invention is shown in FIG.

The phase shifter 3 of FIG. 10 has m delay function gates Δ ₁ to Δ _n having a unit phase delay value Δ for generating signals of various phases, and m for selecting an appropriate phase input among these inputs: It consists of one multiplexer 11, and the unit phase delay value (Δ) of the input data and m: 1 m value of the multiplexer 11 must satisfy Δ × m = 2T (where T is an operation period). .

The retiming clock (phase controlled input data) selected by the m: 1 multiplexer 11 is output to the phase detector 1 and the retiming device 1.

The operation of the digital automatic phase adjustment retiming circuit adopts a method of automatically adjusting the phase of the input clock into the data based on the phase of the input data. Contrary to this configuration, it is based on the input clock rather than the input data. It is also possible to automatically adjust the phase of the input data. An embodiment thereof is shown in FIG. 11, and in comparison with FIG. 1, the configuration of all parts is the same and only the input clock is input to the phase detector and the retiming machine 12. In the loop processor 13 in which the state signals from the phase detector and the retiming unit 12 are input, the phase control signal PCS is outputted to the phase shifter 14 to the phase shifter 14 from the outside. By properly adjusting the phase of the input data inputted to output the phase-controlled input data to the phase detector and the retiming 12 , Based on the input clock different from the one point so that the phase of the input of data retiming in the correct position there is no difference in performance.

As described above, the present invention has an advantage of configuring a digital automatic phase adjustment retiming circuit used to correctly retime data when a clock is given from the outside, and it is easy to manufacture an integrated circuit or a custom semiconductor by using only a digital device. In addition to having a large jitter tolerance, high speed operation is effective.

Claims (4)

The phase of the input data ID is advanced with respect to the retiming clock IC by detecting the phase difference with the retiming clock IC from the phase shifter 3 by receiving the input data ID from the outside. Re-timed data (OD), while outputting phase-state signals (UC), (DC) indicating falling back to loop processor (2), (

) And retimed clock (OC), (

The phase instantaneous signals (UC) and (DC) from the phase detector and the retiming apparatus 1 and the phase detector and the retiming apparatus 1 outputting externally) A loop processor (2) for outputting a phase control signal (PCS) for controlling the phase of the retiming clock to be located at the eye shape center to the phase shifter (3), and a phase control signal (PCS) from the loop processor (2) Digital phase shifter comprising: a phase shifter (3) for receiving a signal and outputting a retiming clock appropriately adjusted to a phase of an input clock input from the outside to the phase detector and the retimer (1) Retiming circuit. A phase state signal (UC) indicating whether the phase of the data is ahead or behind the input clock by detecting the phase difference between each other by receiving an input clock from the outside and receiving phase controlled data from the phase shifter 14; A phase detector and a retiming machine 12 outputting (DC) to the loop processor 13 and outputting the retimed data and a retiming clock to the outside, and inputted from the phase detector and the retiming machine 12; A loop processor 13 for outputting a phase control signal (PCS) for controlling the phase of the input data to the phase shifter 14 so that the significant moment of the input clock is located at the eye-shaped center of the data using the phase state signal; Phase shifter 1 for outputting phase-controlled data to the phase detector and retimer 12, which properly adjusts the phase of input data input from the outside in accordance with the phase control signal PCS from the processor 13 (1). 4) Digital automatic phase control retiming circuit composed of 4) retiming at correct position of input data. 3. The output according to claim 1 or 2, wherein the phase detectors and the retiming apparatuses 1 and 12 are one output of the OR gate OR ₁ to which input data (or an input clock) is input from the outside. ) is a data input terminal of the D-type flip-flop (FF _1), the data input terminal (D) and the exclusive-OR gate (EXOR ₁ and connected to one input the other output (ID-2) a) is a D-type flip-flop (FF ₂₎ ( D) connected to the output of the exclusive-OR gate one input terminal of the (EXOR ₂₎ and the output (S _2-1) the exclusive-OR gate (EXOR ₁₎ is connected to the other input terminal of the D-type flip-flop (FF ₁₎ (S _{2 -2)} is commonly connected to the reset input terminal (R) of the clock input terminal D-type flip-flop (FF ₄₎ of the D flip-flop (FF _3), and output (

The output UC of the flip-flop FF ₃ , which is connected back to the data input terminal D, is output to the loop processors 2 and 13, and the output of the D-type flip-flop FF ₂ that is output to the outside. (OD), (

) Of the outputs (OD), the output (S _2-3) are reset input terminal (R) of the D flip-flop (FF ₃₎ and the D-type flip-peulreup (FF ₄ of the exclusive-OR gate (EXOR ₂₎ is connected to another input terminal Connect to the clock input terminal of common and output (

The output DC of the D-type flip-flop FF ₄ connected with feedback to the data input terminal D is output to the loop processors 2 and 13, and retimed from the phase shifters 3 and 14. The output of the OR gate (OR ₂ ) to which a clock (or phase controlled input data) is input (

) Is connected to the clock input terminal of and the output to the external D-type flip-flop (FF ₁₎ and the other output (OC) is a digital automatic phase control configured hayeoseo connected to the clock input terminal of and the output to the external D-type flip-flop (FF ₂₎ Retiming circuit. 3. The output according to claim 1 or 2, wherein the phase detector and the retiming apparatus (1), (12) have one output (ID-3) of the OR gate (OR ₃ ) to which input data (or an input clock) is input from the outside. ) Is connected to the half-cycle delay circuit 4 while the other output ID-4 is connected to the data input terminal D of the D-type flip-flop FF ₅ , and the output of the half-cycle delay circuit 4 (S _5-2). ) to the output (S _5-3) are D-type flip-flop (the reset input terminal (R) of the clock input terminal and D-type flip-flop (FF ₈₎ of the FF ₇₎ of the exclusive-OR gate (EXOR ₃₎ is connected to one input terminal Connect in common, and output (

The output DC of the D-type flip-flop FF ₇ connected to the data input terminal D is outputted to the loop processors 2 and 13, and the input terminal D of the D-type flip-flop FF ₆ . The output S _5-4 of the exclusive-OR gate EXOR ₄ , with the clock S _5-1 of the D flip-flop FF ₅ connected to one input terminal, is connected to the D flip-flop FF ₇ . Connect to the reset input (R) and the clock input of the D flip-flop (FF ₈ ), and

The output UC of the D flip-flop FF ₈ connected to the data input terminal D is output to the loop processors 2 and 13, and retimed from the phase shifters 3 and 14. Two outputs of the OR gate (OR ₄ ), to which a clock (or phase controlled input data) is input,

) And (OC) are connected to the clock inputs of D flip-flops (FF ₅ ) and (FF ₆ ) while outputting to the outside, respectively, and the two outputs of D flip-flops (FF ₆ ) (

) And (OD) are digital automatic phase control retiming circuits configured by connecting to other input terminals of exclusive OR gates (EXOR ₃ ) and (EXOR ₄ ) while outputting to the outside.

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