KR900007675B1 - Digital Data Phase Adjuster - Google Patents

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Description

Digital Data Phase Adjuster

1 is a block diagram showing the overall configuration of the present invention.

2 is a circuit diagram of a transition detector of the present invention.

3 is a waveform diagram showing the input and output states of the transition detector of the present invention.

4 is a circuit diagram showing the configuration of a transition detector and a transition signal delay line of the present invention.

5 is a circuit diagram showing a phase relationship of a transition detection signal of the present invention.

6 is a circuit diagram of a data and delay line of the present invention.

7 is a waveform diagram showing the phase relationship between the data and the transition detection signal of the present invention.

8 is a circuit diagram showing a phase relationship of a data delay signal of the present invention.

9 is a block diagram showing the configuration of a transition signal delay line and a data delay line and a dual 4: 1 selector of the present invention.

10 is a waveform diagram showing the phase relationship between input signals of a double 4: 1 selector of the present invention.

11 is a waveform diagram showing the phase relationship of the output signal of the double 4: 1 selector of the present invention.

12 is a block diagram showing the configuration of the phase detector of the present invention.

Fig. 13 is a waveform diagram showing input and output states when the phase detector of the present invention operates normally.

14 is a waveform diagram when the phase of the input / output waveform of the phase detector of the present invention is shifted to the right with respect to the reference clock.

Fig. 15 is a waveform diagram when the phase of the input / output waveform of the phase detector of the present invention is shifted to the left with respect to the reference clock.

16 is a circuit diagram showing the configuration of the counter of the present invention.

17 is a waveform diagram showing a state in which data is corrected when a coefficient is reduced in the counter of the present invention.

18 is a circuit diagram showing the configuration of the data reproducing section of the present invention.

Fig. 19 is a waveform diagram showing input and output states of the data reproducing section of the present invention.

Table 1 is a logical table of the transition detector of the present invention.

Table 2 is a logical table of the double 4: 1 selector of the present invention.

* Description of the main parts of the drawings

1: Transition Detector 2: Transition Signal Delay Line

3: Data delay line 4: 2 4: 1 selector

5: phase detector 6: counter

7: data reproducing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data phase adjuster, and more particularly, to a digital data phase adjuster for easily synchronizing a clock and data and reproducing data compared to a conventional synchronous method using an analog element using only a digital element.

In general, the data phase season is always synchronized with the reference clock when the digital signal processing is performed in the switching network of the repeater or the exchange. It is a known fact that the clock causes data to be regenerated at the center of the data by adjusting the phase of the data.

Conventionally, in the switching network of a repeater or an exchange, the clock prevents the data from being fetched at the transition part of the data, and the phase of the data is adjusted so that the data is always fetched from the center of the data to prevent the occurrence of error data and to prevent the left and right movement of the data. The data phase adjuster was constructed using only an analog device to remove and reproduce normal data.

Therefore, the conventional data phase regulator, which is a phase locked loop (PLL) using an analog device such as a voltage controlled oscillator (VCO) or a loop filter, has a problem in that its manufacture is complicated and not easy to integrate.

Accordingly, an object of the present invention is to provide a digital data phase adjuster that is easy to manufacture and simple to synchronize.

The present invention will be described in detail with reference to the accompanying drawings as follows.

Transition detector (1) which receives input data (IC) from the outside and detects the moment of data transition, that is, the moment of change from low to high or high to low, and outputs a square wave having a constant width, Transition signal delay line 2 for outputting the transition detection signal T0 inputted from the transition detector 1 and the transition output signals T1, T2, and T3 having a delay time of a predetermined time. ) And output signals D1, D2, and D3 in which the input data ID from the outside has a data signal D0 input through the delay circuit K and a delay time by a predetermined time. The data delay line 3 which outputs?), The transition signals T0 to T3 of the transition signal delay line 2 and the data signals D1 to D3 of the data delay line 3 are inputted. A dual 4: 1 selector for selecting and outputting one of the transition and data signals by the control signal from the handwriting 6 (Dual 4: One selector (4) and one of the transition signals (T0) to (T3) from the dual 4: 1 selector (4) are input and sampled using the reference clock (CK +) and the inverted clock (CK-). A phase detector (5) for outputting a counter control signal and a binary output according to the counter control signal from the phase detector (5), and the control signal is transferred to a double 4: 1 selector (4). One of the output counter (6) and one of the data signals (D0) to (D3) from the 4: 1 selector (4) is input and the reference clock (CK +) via the delay circuit (a). And data regeneration units 7 for sampling using the inverted click K− and outputting the output data 0D synchronized with the reference clock CK +.

FIG. 2 shows the configuration of the transition detector 1. The transition detection signal is output from the output terminal by allowing the input data ID from the outside to pass through the delay circuit D or directly to both sides of the exclusive logic sum gate EXOR1. (T0) is output.

Therefore, as shown in FIG. 3, input data ID having a value of LOW for a width W, which is a predetermined period (t1 to t2), is directly input through the delay circuit D (X1). There is a phase difference from (X2) by the delay time α in the delay circuit D, and the exclusive logic sum gate EXOR1 to which the two signals X1 and X2 are input is shown in Table 1 (logical table). As shown in Fig. 2), when the value 1 of the input 1 is odd, the value 1 is outputted. Therefore, the transition detection signal T0, which is the output of the exclusive logic sum gate exor1, is transmitted by the delay circuit D. It outputs a square wave having a high value during the delay, that is, between t1 and t1 + α and only between t2 and t2 + α.

The delay time α can be arbitrarily set according to the width W of the input data ID.

4 shows the configuration of the transition detector 1 and the transition signal delay line 2. The transition detection signal T0, which is the output of the exclusive logic sum gate EXOR1 of the transition detector 1, is transmitted to the delay circuit a1. The transition output signal T1 delayed by the delayed transition signal, the transition output signal T2 delayed by the delay circuit a2 and the transition output signal T3 delayed by the delay circuit a3 again together with the transition detection signal T0. It is to be output to the dual 4: 1 selector (4).

Therefore, as shown in FIG. 5, the transition detector signal T0 through which the input data ID from the outside passes through the transition detector 1 is equal to the delay time α from the transition times t1 and t2. Transition output which is a square wave having a width of and the delay detection signal T0 is sequentially delayed by the delay time a, a2, or a3 by the delay circuits a1, a2, and a3. The signals T1, T2, and T3 are square waves in which the transition detection signal T0 is delayed by the delay times a, 2a, and 3a, respectively, and the transition detection signal T0 and the transition output are described above. The signals T1, T2, and T3 are output to the dual 4: 1 selector 4.

Here, the delay period (a) is set to a value corresponding to 1/4 of the width (W) of the data, and the delay time (α) is set to a value smaller than the delay time (a).

6 shows the configuration of the data delay circuit 3. The data signal D0 delayed by the delay time K while the input data ID passes through the delay circuit K, and the data signal D0 are delayed. The data output signal D1 delayed by the delay time a by the circuit a4, the data output signal D2 delayed by the delay time a again by the delay circuit D5, and The data output signal D3 is delayed by the delay circuit D6 again by the delay time a so that all of the data output signals D3 are output to the dual 4: 1 selector 4.

Therefore, the data signal D0 whose input data ID from the outside has been delayed by the delay circuit K by the delay time K = α / 2 is outputted from the transition detector 1 as shown in FIG. The transition instant is made at the middle of the width? Of the high value of the transition detection signal T0.

Then, as shown in FIG. 8, the data signal D0 delayed by the delay time K from the input data ID, and the input data ID by the delay circuits a4, a5, and a6. The data output signals D1, D2, and D3 delayed by (K + a), (K + a2), and (K + 3a), respectively, are output to the dual 4: 1 selector (4). 9 shows the configuration of a dual 4: 1 selector, which is sequentially delayed by the delay circuits a1, a2, and a3 together with the transition detection signal T0. ), (T3) is input to the input terminals Ti0, (Ti1), (Ti3) and the delay circuits a4, a5, together with the 4: 1 transition signal selector 4a and the data signal D0. 4: 1 data selection unit 4b, in which the data output signals D1, D2, and D3 sequentially delayed by (a6) are input to the input terminals D10, D11, D12, and D13. The dual 4: 1 selector (4) is composed of a 4: 1 transition signal selector (4a) and a 4: 1 data selector by the control signals (S0) and (S1) input from the counter (6). Four signals (T0), (T1), (T2) input to (4b) .T4, and one of (D0), (D1), (D2), and (D3) is output to (Zt) and (Zd). )

Therefore, the transition signals (T0), (T1), (T2), and (4) input to the 4: 1 transition signal selector 4a and 4: 1 data selector 4b of the dual 4: 1 selector 4 respectively. T3) and the data signals D0, D1, D2, and D3 are data signals D0 and delay time in which the input data 1D is delayed by the delay time K, as shown in FIG. Transition with the data output signals D1, D2, D3 delayed by the delay times a, 2a, and 3a in the transition detection signal T0, which is a square wave having a width of (α), respectively. Since the output signals are T1, T2, and T3, the same phase relationship is always maintained. Accordingly, the 4: 1 transition signal selection unit 4a and the data selection unit 4b are commonly input to the control signal S0. ) And (S1) have the same operating characteristics. In addition, the control signals S0 and S1 input from the counter 6, which is a binary counter, have control signals S0, S1 as (OQ), (01), Transition detection signal T0 and data signal D0 and transition output signal T1 at the two output terminals Zt and Zd of the dual 4: 1 selector 4 according to (1.0) and (1.1). And the data output signal D1, the transition output signal T2 and the data output signal D2, the transition output signal T3 and the data output signal D3 are output, respectively, as shown in FIG. The transition of the data signal Dx occurs at the midpoint of the width? Where Tx has a high value. Where X is 0.1.2.3

12 shows the configuration of the phase detector 5. The output terminal Zt of the 4: 1 transition signal selector 4a of the dual 4: 1 selector 4 is connected to the input terminals D1 and D2. The reference clock CK + and the inverted clock CK- are input to the clock terminals CP1 and CP2 of the two flip-flops FF1 and FF2, respectively, so that the two flip-flops FF1 and FF2 are respectively input. The counter control signals QL and QR are outputted at the output terminals Q1 and Q2, respectively.

Therefore, when the phase detector 5 operates normally, as shown in FIG. 13, both the reference clock CK + and the inverted clock CK- are placed in the protection region of the transition signal Tx (where X is 0.1.2.3). The base relationship of denture is maintained, and accordingly, the values (1, 2) of the counter control signals QL and QR which are outputs of the two flip-flops FF1 and FF2 of the phase detector 5 are always the same. It will have a value (here LOW).

Therefore, the delay clock CKm for reproducing the output of the data reproducing section 7, which will be described later, has a phase located in the center of the data signal Dx outputted from the output terminal Zd of the dual 4: 1 selector 4. Since the data reproducing section 7 can output the output data 0D without error, and the values of the counter control signals QL and QR do not change, the output terminal Zt of the dual 4: 1 output unit 4 is output. In Zd, the current state is maintained.

If the phase is out of phase relation by the jitter component in which the magnitude of the waveform is modulated on the visual axis and the signal shakes left and right, the transition signal Tx and the data signal Dx, which are outputs of the double 4: 1 selector 4 Is moved to the right relative to the reference clock (ck +) (Fig. 14 waveform), or to the left (Fig. 15 waveform) so that the reference clock (CK +) or inverted clock (CK-) is at the left and right boundaries. It is located in the region α.

In this phase relationship, when the output of the 4: 1 transition signal selection section 4a selects the transition signal Tx by using the reference clock CK + and the inverted clock CK- of the phase detector 5, the signal is shifted to the right. In the case of FIG. 14 shifted, the sampling value of the reference clock CK + becomes high. The sampling value of the inverted clock CK- becomes LOW. In the case of FIG. 15 shifted to the left, sampling by the reference clock CK +. The value is LOW and the sampling value by the inverted clock (CK-) becomes High and appears differently.

Therefore, the value of the delay time α of the transition signal Tx is close to the transition point of the data signal Dx of which the reference clock CK + or the inverted clock CK- is the output of the 4: 1 data selector 4b. To determine the left and right deviations (maximum d = 2a-k, k = α / 2) that the delay clock CKm can move from the center of the data signal Dx (d = 2a). It is determined by considering the data transmission speed (1 / w, w = 4a) and the allowance of data as variables.

Therefore, in the case of moving to the right as shown in FIG. 14, the delay clock CKm is sampled near the transition of the data signal Dx. Accordingly, the delay clock CKm is caused by the confusion of the data signal Dx. Since the probability of generating error data increases, the data signal Dx and the transition signal Tx are shifted to the left in order to keep the delay clock CKm more stable at the transition point of the data signal Dx. The data signal Dx, which is the output of the 4: 1 selector 4, must be changed to the value of the input terminal D1x-1, and the transition signal Tx must also be changed to the value of the input terminal T1x-1. Therefore, the counter control signal QL is output to High so that the control signals S0 and S1 which are the outputs of the counter 6 are reduced.

In the case of moving to the left as shown in FIG. 15, the data signal Dx is the value of the input terminal D1x + l, and the transition signal Tx is the same as that of FIG. Since it needs to be converted to a value, the counter control signal (OR) is output high.

16 shows the configuration of the counter 6, in which the counter control signals QL and OR respectively input to the down terminal DOWN and the up terminal UP of the counter 6a are exclusive logical sum gates EXOR2. The control signals S0 and S1 are outputted from the output terminals P0 and P1 of the counter 6a by being applied to the clock terminal CP via.

Therefore, when the counter control signal QL is input high to the down terminal DOWN of the counter 6a and the counter control signal QR is input low to the up terminal UP, the two counter control signals QL and QR are inputted. ) Is applied to the clock terminal CP at high while passing through the exclusive OR gate EXOR2, and the control signals S0 and S1 output from the output terminals P0 and P1 of the counter 6a are reduced. On the other hand, when the two counter control signals QL and QR are applied to the values LOW and High, respectively, the output of the counter 6a outputs the control signals S0 and S1 in an increased state. do.

FIG. 17 shows a process of correcting the state shifted to the right as shown in FIG. 14. The reference clock CK + is applied to the transition point of the data signal Dx and the boundary region α of the transition signal Tx. When the inverted clock CK- is positioned, the counter control signals QL and QR are input from the phase detector 5 to High and LOW, respectively, and High is also input to the output terminal CP. ) And (S1) are reduced to the data signal DX-1 and the transition signal TX which are output to the dual 4: 1 selector 4 and input to the previous input terminal Dix-1 (T1x-1). -1) is output from the double 4: 1 selector 4 so that the reference clock CK + and the inverted clock CK- are in a normal state located in the protection area of the transition signal TX-1.

18 shows the configuration of the data reproducing section 7. The flip-flop FF3 is connected to the output terminal Zd and the input terminal D3 of the 4: 1 data selecting section 4b of the dual 4: 1 selector 4. The delay clock (CKm) whose reference clock (CK +) is delayed by the delay time (a) by the delay circuit (a) is input to the clock terminal (CP3) of the terminal), and the output terminal Q3 and the input terminal of the flip-flop FF3 are input. The inverted clock CK- is input to the clock terminal CP4 of the flip-flop FF4 to which the D4 is connected, and the flip-flop FF5 to which the output terminal Q4 and the input terminal D5 of the flip-flop FF4 are connected. The reference clock CK + is inputted to the clock terminal CP6 of the output terminal 0D at the output terminal Q5 thereof so as to be output to the outside.

Therefore, in the data reproducing section 7, a waveform in which the data signal DX output from the data selecting section 4b is shifted at the rising edge of the delay output DKm as shown in FIG. 19 is flip-flop FF3. A waveform that is output from the output terminal Q3 of the output signal and shifted from the upper edge of the inverted clock CK- to the flip-flop FF4 is output from the output terminal 4 of the flip-flop FF5, and then again flip-flop ( The output data 0D, which is shifted at the rising edge of the reference clock CK + of FF5, is output from the output terminal Q5 so that the output data 0D synchronized with the reference clock CK + is outputted as a synchronization signal.

In this case, by using the inverted clock CK- to compensate for the set-up time of the reference clock CK +, the output data 0D perfectly synchronized to the reference clock CK + is output. .

Claims (2)

Transition detector 1 which consists of delay circuit D and exclusive OR gate EXOR1 and detects the transition moment of input data ID and outputs the transition detection signal T0, and the transition from transition detector 1 Transition signal delay line 2 for outputting the detection signal T0 and the transition output signals T1, T2, and T3 sequentially delayed by the delay circuits a1, a2, and a3. And the data signal D0 whose input data ID is delayed by the delay circuit K and the data output signal D1 which is sequentially delayed by the delay circuits a4, a5 and a6. The data delay line 3, which outputs D2) and D3, the transition detection signal T0 from the transition signal delay line 2, and the transition output signals T1, T2, and T3 are 4: 1 The data signal D and the data output signal D1 from the data delay line 3 are inputted to the input terminals T10, T11, T12 and T13 of the transition signal selection section 4a. (D2) and (D3) are input to the 4: 1 data selector 4b. One of the transition signals T0 to T3 and the data signals D0 to D3 is output to the output terminal Zt by the control signals S0 and S1 which are commonly input from the handwriting 6; Two flip flips (FFl) connected to a dual 4: 1 selector (4) output to (Zd) and the output terminal (Zt) and the input terminals (D1) and (D2) of the above 4: 1 transition signal selection unit (4a). Counter clock CK + and inverted clock CK- are inputted to clock terminals CP1 and CP2 of FF2 and counter control signals QL and Q2 at output terminals Ql and Q2. The phase detector 5 and the counter control signals QL and QR from the phase detector 5 are inputted to the down terminal DOWN and the up terminal UP, respectively. A counter 6 for outputting the control signals S0 and S1 from the output terminals P0 and P1 of the counter 6a, which are input to the clock terminal CP via EXOR2, and the above-mentioned counters. 4: 1 Clock terminal of flip-flop FF3 with output terminal Zd and input terminal D3 of data selection unit 4b connected When the delay clock CKm via the delay circuit a is input to the child CP3, the output terminal Q3 and the input terminal D4 are connected, and the inverted clock CK- is input to the clock terminal CP4. The output terminal Q4 of the flip-flop FF4 is connected to the input terminal D5 of the flip-flop FF5 to which the reference clock CK + is input to the clock terminal CP5, so that the output data 0D is output from the output terminal Q5. A digital data phase adjuster characterized in that it is composed of data reproducing units (7) for output. The phase detector 5 compares the phase of the transition signal Tx and the reference clock CK + and shifts one of the counter control signals QL and QR as it is moved to the left and right of the phase. Counter 6 which is outputted as high and input to clock terminal CP via exclusive logic sum gate EXOR2 while counter control signals QL and QR are input to down terminal DOWN and UP terminal UP. In this case, as the two control signals QL and QR are applied as high, the delay time is inputted to the dual 4: 1 selector 4 in a state in which the control signals S0 and S1 are decreased or increased. Outputs the output data (0D) by synchronizing the input data (ID) with the reference clock (CK +) in the normal state by outputting the transition signal (Tx) and the data signal (Dx) moved left or right by (a). A digital data phase adjuster for output from the playback unit (7).

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