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KR900007118A - Nonvolatile Semiconductor Memory and Manufacturing Method - Google Patents

Nonvolatile Semiconductor Memory and Manufacturing Method Download PDF

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Publication number
KR900007118A
KR900007118A KR1019890015036A KR890015036A KR900007118A KR 900007118 A KR900007118 A KR 900007118A KR 1019890015036 A KR1019890015036 A KR 1019890015036A KR 890015036 A KR890015036 A KR 890015036A KR 900007118 A KR900007118 A KR 900007118A
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South Korea
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insulating film
polysilicon layer
resist
forming
region
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KR1019890015036A
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Korean (ko)
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KR920010317B1 (en
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아츠시 소지
미치하루 이나미
마사미치 아사노
다다시 미야카와
다다유키 다우라
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로일렉트로닉스 가부시키가이샤
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Publication of KR900007118A publication Critical patent/KR900007118A/en
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Publication of KR920010317B1 publication Critical patent/KR920010317B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/689—Vertical floating-gate IGFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

내용 없음.No content.

Description

불휘발성 반도체기억장치 및 그 제조방법Nonvolatile Semiconductor Memory and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 따른 불휘발성 반도체기억장치의 평면도.1 is a plan view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

제2도는 제1도의 단면(A-A′)에 따른 단면도.FIG. 2 is a cross sectional view along section A-A 'of FIG. 1;

제3도는 제1도의 단면(B-B´)에 따른 단면도.3 is a sectional view taken along the section B-B 'of FIG.

Claims (4)

불휘발성 반도체메모리셀이 행렬상태로 배열되어 이루어진 셀어레이를 갖춘 불휘발성 반도체기억장치에 있어서, 반도체기판(1)내에 소오스/드레인영역(2)이 형성되어 있고, 상기 반도체기판(1)내의 채널영역이 상기 소오스/드레인영역(2)간에 배치되며, 부유게이트(6)가 제1 게이트절연막(5)을 매개해서 반도체기판(1) 표면에 형성되고, 이 부유게이트(6)의 길이가 상기 채널영역의 길이보다 짧으며, 이 채널영역상의 소오스/드레인영역(2)의 어느 한쪽의 부근에 부유게이트(6)가 존재하지 않는 오프셋부를 갖추고 있고, 이 오프셋부에는 제어게이트(8)가 제2게이트절연막(7)을 매개해서 채널영역의 일부영역과 대향되게 설치되어 있으며, 상기 채널영역의 폭방향에 인접한 메모리셀트랜지스터의 드레인영역 및 소오스영역이 각각 공통으로 형성되어 있고, 상기 메모리셀트랜지스터는 부유게이트(6) 혹은 제어게이트(8)와 자기정합적으로 형성된 소자분리영역(3)에 의해 분리되어 있으며, 상기 제어게이트(8)가 소오스/드레인영역(2)과 직교하도록 된 것을 특징으로하는 불휘발성 반도체기억장치.In a nonvolatile semiconductor memory device having a cell array in which nonvolatile semiconductor memory cells are arranged in a matrix state, source / drain regions 2 are formed in the semiconductor substrate 1, and channels in the semiconductor substrate 1 are formed. A region is disposed between the source / drain regions 2, and floating gates 6 are formed on the surface of the semiconductor substrate 1 via the first gate insulating film 5, and the length of the floating gates 6 It is shorter than the length of the channel region, and has an offset portion in which no floating gate 6 exists near one of the source / drain regions 2 on the channel region. It is provided so as to face a portion of the channel region via the two-gate insulating film 7, and the drain region and the source region of the memory cell transistor adjacent to the width direction of the channel region are formed in common, respectively. The memory cell transistor is separated by an isolation region 3 formed self-aligned with the floating gate 6 or the control gate 8 so that the control gate 8 is orthogonal to the source / drain region 2. Nonvolatile semiconductor memory device characterized in that. 제1항에 있어서, 채널폭방향에 인접한 2개의 메모리셀트랜지스터중 한쪽 메모리셀트랜지스터의 소오스영역역과 공통으로 형성되어 있는 것을 특징으로 하는 불휘발성 반도체기억장치.The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed in common with the source region of one of the two memory cell transistors adjacent to the channel width direction. 제1도전형의 반도체기판(1)상에 제1절연막(5)을 형성시키는 공정과, 전면에 제1 폴리실리콘층(6)을 형성시키는 공정, 이 제1 폴리실리콘층(6)을 소정형상으로 패터닝하는 공정, 이 패터닝된 제1 폴리실리콘층(6)을 마스크로 이용해서 반도체기판(1)에 제2 도전형의 불순물을 이온주입하는 공정, 이 불순물을 활성화시키는 공정, 전면에 제2절연막(4)을 형성시키는 공정, 전면에 제1 레지스트(9)를 도포하는 공정, 이 제1 레지스터(9) 및 제2 절연막(4)을 상기 제1 폴리실리콘층(6)과 같은 높이를 엣칭하는 공정, 전면에 제2 레지스트(10)를 도포하는 공정, 이 제2 레지스트(10)를 소정의 형상으로 패터닝하는 공정, 이 패터닝된 제2 레지스트(10)를 마스크로 이용해서 상기 제1 폴리실리콘층(6) 및 제1 절연막(5)을 제거하는 공정, 전면에 제3절연막(7)을 형성시키는 공정, 전면에 제2 폴리실리콘층(8)을 형성시키는 공정, 이 제2 폴리실리콘층(8)및 제3절연막(7), 제1 폴리실리콘층(6) 및 제1 절연막(5)을 소정의 형상으로 패터닝하는 공정, 상기의 공정에서 소정형상으로 패터닝된 부분 및 제2 절연막(4)을 마스크로 이용해서 제1 도전형의 불순물을 이온주입하는 공정, 이 제1 도전형의 불순물을 활성화시키는 공정을 구비한 것을 특징으로 하는 전기적기억소거가 가능한 불휘발성 반도체기억장치의 제조방법.A step of forming the first insulating film 5 on the first conductive semiconductor substrate 1, a step of forming the first polysilicon layer 6 on the front surface, and the first polysilicon layer 6 are prescribed. Patterning into a shape, ion implanting a second conductivity type impurity into the semiconductor substrate 1 using the patterned first polysilicon layer 6 as a mask, activating the impurity, (2) forming the insulating film (4), applying the first resist (9) to the entire surface, and placing the first resistor (9) and the second insulating film (4) at the same height as the first polysilicon layer (6). Etching, coating the second resist 10 on the entire surface, patterning the second resist 10 into a predetermined shape, and using the patterned second resist 10 as a mask. 1 removing the polysilicon layer 6 and the first insulating film 5, forming the third insulating film 7 on the entire surface, all Forming the second polysilicon layer 8 on the second polysilicon layer 8, the third polysilicon layer 8 and the third insulating film 7, the first polysilicon layer 6 and the first insulating film 5 A step of ion implanting impurities of the first conductivity type using a portion patterned in a predetermined shape and the second insulating film 4 as a mask in the above process, and activating the impurities of the first conductivity type Method of manufacturing a nonvolatile semiconductor memory device capable of electrical memory erasure, characterized in that it comprises a. 제1도전형의 반도체기판(1)상에 제1절연막(5)을 형성시키는 공정과, 전면에 제1폴리실리콘층(6)을 형성시키는 공정, 이 제1폴리실리콘층(6)을 소정형상으로 패터닝하는 공정, 이 패터닝된 제1폴리실리콘층(6)을 마스크로 이용해서 반도체기판(1)에 제2 도전형의 불순물을 이온주입하는 공정, 이 불순물을 활성화시키는 공정, 전면에 제2 절연막(4)을 형성시키는 공정, 전면에 제1레지스트(9)를 도포하는 공정, 이 제1레지스트(9) 및 제2 절연막(4)을 상기 제1폴리실리콘층(6)과 같은 높이를 엣칭하는 공정, 전면에 제2레지스트(10)를 도포하는 공정, 이 제2레지스트(10)가 제1폴리실리콘층(6)상에만 잔류하도록 엣칭하는 공정, 이 패터닝된 제2레지스트(10)를 마스크로 이용해서 제1폴리실리콘층(6) 및 제1절연막(5)이 그 약측의 제2절연막(4)과 떨어져 위치하도록 하는 공정, 이 떨어져 위치한 영역의 한쪽의 빈 영역을 제3레지스트(11)로 피복하는 공정, 다른 한쪽의 빈 영역에 제2도전형의 불순물을 이온주입하는 공정, 이 제2도전형의 불순물을 활성화시키는 공정, 전면에 제3절연막(7)을 형성시키는 공정, 전면에 제2폴리실리콘층(8)을 형성시키는 공정, 이 제2폴리실리콘층(8) 및 제3절연막(7), 제1폴리실리콘층(6) 및 제1절연막(5)을 소정의 형상으로 패터닝하는 공정, 이 소정형상으로 패터닝된 부분 및 제2절연막(4)을 마스크로 이용해서 제1도전형의 불순물을 이온주입하는 공정, 이 제1도전형의 불순물을 활성화시키는 공정을 구비하는 것을 특징으로 하는 전기적기억소거가 가능한 불휘발성 반도체기억장치의 제조방법.A step of forming the first insulating film 5 on the first conductive semiconductor substrate 1, a step of forming the first polysilicon layer 6 on the front surface, and the first polysilicon layer 6 are prescribed. A step of patterning into a shape, a step of ion implanting a second conductivity type impurity into the semiconductor substrate 1 using the patterned first polysilicon layer 6 as a mask, a step of activating this impurity, 2 A step of forming the insulating film 4, a step of applying the first resist 9 to the entire surface, the first resist 9 and the second insulating film 4 the same height as the first polysilicon layer 6 Etching step, applying the second resist 10 to the entire surface, etching the second resist 10 so that it remains only on the first polysilicon layer 6, and the patterned second resist 10 Is used as a mask so that the first polysilicon layer 6 and the first insulating film 5 are separated from the second insulating film 4 on its weak side. To cover one empty region of the separated region with a third resist 11, ion implantation of a second conductive type impurity into the other empty region, and to activate the second conductive type impurity. Step, forming a third insulating film 7 on the entire surface, forming a second polysilicon layer 8 on the entire surface, the second polysilicon layer 8 and the third insulating film 7, the first poly A step of patterning the silicon layer 6 and the first insulating film 5 into a predetermined shape, and ion implantation of impurities of the first conductive type using the portion patterned in the predetermined shape and the second insulating film 4 as a mask. And a step of activating the impurity of the first conductivity type, wherein the nonvolatile semiconductor memory device is capable of electrically erasing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890015036A 1988-10-19 1989-10-19 Non-volatile semiconductor memory device and its manufacturing method KR920010317B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP88-263166 1988-10-19
JP63-263166 1988-10-19
JP63263166A JPH0760866B2 (en) 1988-10-19 1988-10-19 Method of manufacturing nonvolatile semiconductor memory device

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KR900007118A true KR900007118A (en) 1990-05-09
KR920010317B1 KR920010317B1 (en) 1992-11-26

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US5512505A (en) * 1990-12-18 1996-04-30 Sandisk Corporation Method of making dense vertical programmable read only memory cell structure
US5343063A (en) * 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
JP2003222124A (en) 1999-07-14 2003-08-08 Sumitomo Electric Ind Ltd Spindle motor
US6868015B2 (en) * 2000-09-20 2005-03-15 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with control gate spacer portions
US7064978B2 (en) * 2002-07-05 2006-06-20 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM

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KR920010317B1 (en) 1992-11-26
JPH0760866B2 (en) 1995-06-28
JPH02110980A (en) 1990-04-24

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