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KR960026771A - Non-volatile memory device manufacturing method - Google Patents

Non-volatile memory device manufacturing method Download PDF

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Publication number
KR960026771A
KR960026771A KR1019940034568A KR19940034568A KR960026771A KR 960026771 A KR960026771 A KR 960026771A KR 1019940034568 A KR1019940034568 A KR 1019940034568A KR 19940034568 A KR19940034568 A KR 19940034568A KR 960026771 A KR960026771 A KR 960026771A
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South Korea
Prior art keywords
polysilicon layer
bit line
etching process
memory device
self
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KR1019940034568A
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Korean (ko)
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KR100309139B1 (en
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장희현
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김주용
현대전자산업 주식회사
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Priority to KR1019940034568A priority Critical patent/KR100309139B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 비휘발성 메모리 소자의 제조방법에 관한 것으로, 전기적으로 프로그램(Program) 및 소거(Erase) 특성을 갖는 메모리 셀 제조에서 비트라인(Bit Line)을 공유하는 인접 셀의 컨트롤 게이트를 비트라인 콘택부를 제외한 전체 메모리 셀 어레이(Array)에 걸쳐 하나의 선으로 연결하므로써 컨트롤 게이트의 저항을 줄이고, 측면 캐패시터를 이용하여 컨트롤 게이트와 플로팅 게이트간의 커플링 비를 개선시키며, 비트라인은 각 단위 셀의 드레인을 형성할 때 동시에 드레인 연결용 확산층을 형성함으로써 소자의 신뢰성 및 수율을 향상시킬 수 있는 비휘발성 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, wherein the control gate of a neighboring cell sharing a bit line is a bit line contact in a memory cell fabrication having electrically programmed and erased characteristics. One line across the entire memory cell array, except for negative, reduces the resistance of the control gate and improves the coupling ratio between the control and floating gates by using side capacitors. The present invention relates to a method of manufacturing a nonvolatile memory device capable of improving the reliability and yield of a device by forming a diffusion layer for drain connection at the same time.

Description

비휘발성 메모리 소자 제조방법Non-volatile memory device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2,3,4도는 본 발명에 따라 공정단계별로 도시한 레이아웃도, 제2A 및 2B도는 제2도의 X-X′및 Y-Y′선을 따라 절단한 소자의 단면도, 제3A 및 제 3B도는 제3도의 X-X′및 Y-Y′선을 따라 절단한 소자의 단면도, 제4A 및 4B도는 제4도의 X-X′ 및 Y-Y′선을 따라 절단한 소자의 단면도.2, 3, and 4 are layout views showing process steps in accordance with the present invention, and FIGS. 2A and 2B are cross-sectional views of elements cut along the lines XX 'and YY' of FIG. 2, and FIGS. 3A and 3B are shown in FIG. Sectional drawing of the element cut along the lines XX 'and YY', FIGS. 4A and 4B are sectional views of the element cut along the lines XX 'and YY' of FIG.

Claims (11)

비휘발성 메모리 소자 제조방법에 있어서, 실리콘 기판에 활성영역과 비활성영역을 확정한 후 필드 산화막을 성장시키고, 터널 산화막과 제1폴리실리콘층을 형성하는 단계와, 상기 단계로부터 제1폴리실리콘층을 1차 식각한 후 불순물 이온주입공정으로 비트라인을 형성하는 단계와, 상기 단계로부터 층간 절연막 및 제2폴리실리콘층을 형성한 후 자기정렬 식각공정으로 상기 1차 식각된 제1폴리실리콘층과 제2폴리실리콘층을 식각하는 단계와, 상기 단계로부터 불순물 이온주입공정으로 소오스라인을 형성하는 단계로 이루어지는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.In the method of manufacturing a nonvolatile memory device, after the active region and the inactive region are determined on a silicon substrate, a field oxide film is grown, a tunnel oxide film and a first polysilicon layer are formed, and the first polysilicon layer is formed from the step. Forming a bit line by an impurity ion implantation process after the first etching, and forming an interlayer insulating film and a second polysilicon layer from the step, and then forming the first polysilicon layer and the first etched layer by the self-aligned etching process. And (2) etching the polysilicon layer, and forming a source line through the impurity ion implantation process from the step. 제1항에 있어서, 상기 활성영역은 트랜지스터의 채널, 드레인 비트라인 및 소오스라인이 되어질 부분으로 확정되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein the active region is determined as a portion of a transistor to be a channel, a drain bit line, and a source line. 제1항에 있어서, 상기 비트라인은 각 단위 셀의 드레인과 이 드레인간을 연결해 주는 확산층으로 이루어지는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein the bit line comprises a diffusion layer connecting the drain of each unit cell to the drain. 제1항에 있어서, 상기 자기정렬 식각공정을 통해 제2폴리실리콘층을 식각하여 소자의 컨트롤 게이트를 형성하되, 이 컨트롤 게이트는 비트라인을 공유하는 인접 셀에 공통 컨트롤 게이트로 형성되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein the second polysilicon layer is etched through the self-aligned etching process to form a control gate of the device, wherein the control gate is formed as a common control gate in an adjacent cell sharing a bit line. A nonvolatile memory device manufacturing method. 제4항에 있어서, 상기 공통 컨트롤 게이트는 비트라인 콘택부를 제외한 전체 메모리셀 어레이에 걸쳐 하나의 선으로 형성되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 4, wherein the common control gate is formed as one line over the entire memory cell array except for the bit line contact unit. 제1항에 있어서, 상기 제1폴리실리콘층은 비트라인 영역이 개방되게 하는 1차 식각공정으로 한쪽 측면을 확정하고, 다른 한쪽 측면을 자기정렬 식각공정을 통해 확정하여 소자의 플로팅 게이트를 형성시키는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein one side of the first polysilicon layer is determined by a first etching process in which a bit line region is opened, and the other side is determined through a self-aligned etching process to form a floating gate of the device. Method for manufacturing a nonvolatile memory device, characterized in that. 제6항에 있어서, 상기 플로팅 게이트는 제1폴리실리콘층의 1차 식각공정후에 실시하는 자기정렬 식각공정에 의해 그 선폭이 결정되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 6, wherein the floating gate has a line width determined by a self-aligned etching process performed after the first etching process of the first polysilicon layer. 제1항에 있어서, 상기 제1폴리실리콘층의 1차 식각공정으로 노출된 활성영역은 상기 제2폴리실리콘층에 의해 상기 자기정렬 식각공정으로부터 손상이 방지되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The nonvolatile memory device of claim 1, wherein the active region exposed by the first etching process of the first polysilicon layer is prevented from damaging the self-aligned etching process by the second polysilicon layer. Way. 제1항에 있어서, 상기 제1폴리실리콘층의 식각에 의해 형성된 제1폴리실리콘층의 드레인 측면이 상기 제2폴리실리콘층으로 덮히게 하는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein the drain side surface of the first polysilicon layer formed by etching the first polysilicon layer is covered with the second polysilicon layer. 제9항에 있어서, 상기 제1폴리실리콘층 및 상기 제2폴리실리콘층 사이는 층간 절연막이 형성되는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.10. The method of claim 9, wherein an interlayer insulating film is formed between the first polysilicon layer and the second polysilicon layer. 제1항에 있어서, 상기 제1폴리실리콘층의 1차 식각공정으로 노출된 활성영역이 후속되는 이온주입공정에 의해 추가의 사전공정없이 소오스라인과 독립적으로 비트라인을 형성하는 것을 특징으로 하는 비휘발성 메모리 소자 제조방법.The method of claim 1, wherein the active region exposed by the first etching process of the first polysilicon layer is formed by the ion implantation process followed by the ion implantation process to form a bit line independently of the source line without any further preliminary process. Method of manufacturing volatile memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034568A 1994-12-16 1994-12-16 Non-volatile memory device manufacturing method KR100309139B1 (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US6268622B1 (en) 1998-07-13 2001-07-31 Samsung Electronics Co., Ltd. Non-volatile memory device and fabrication method thereof

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KR100485502B1 (en) * 2002-09-19 2005-04-27 동부아남반도체 주식회사 Nonvolatile memory device and method for manufacturing thereof

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JPS6418270A (en) * 1987-07-13 1989-01-23 Oki Electric Ind Co Ltd Semiconductor memory device
JPH0278276A (en) * 1988-09-14 1990-03-19 Hitachi Ltd semiconductor equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268622B1 (en) 1998-07-13 2001-07-31 Samsung Electronics Co., Ltd. Non-volatile memory device and fabrication method thereof
KR100316709B1 (en) * 1998-07-13 2001-12-12 윤종용 Fabrication method of non-volatile memory device
US6521495B2 (en) 1998-07-13 2003-02-18 Samsung Electronics Co., Ltd. Method of fabricating a non-volatile memory device

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