KR900005799B1 - Personal computer input / output scanning device - Google Patents

Abstract

No content.

Description

Personal computer input / output scanning device

1 is a block diagram showing a method of interfacing with a conventional personal computer and an input / output device.

2 is a block diagram showing a conventional personal computer, an input / output device, and a method of extending the input / output.

3 is a block diagram of an input / output scanning device of the present invention.

4 is a block diagram of control logic of the present invention.

* Explanation of symbols for main parts of the drawings

A: I / O scan circuit 6,7,8: Bus buffer

4: First-in-first-out memory 5: First-in-first-out address control logic

3: internal memory 2: control logic

9: buffer 1: microprocessor

The present invention allows an input / output scan between a personal computer and an input / output device such as IBM-PC or IBM-PC / AT to be performed by its own microprocessor without interference of the central processing unit (CPU) in the personal computer. The present invention relates to a personal computer input / output scanning device capable of improving the processing speed.

In the conventional input / output interface method, as shown in FIG. 1, the central processing unit in the personal computer (PC) directly controls and addresses the input / output device through the bus buffer, and inputs and outputs data, because of the limitation of the address area of the personal computer itself. The I / O score that can be processed is small, and the burden ratio by the direct I / O management of the central processing unit is increased, thereby reducing the efficiency of the central processing unit. In the method shown in FIG. 2, the central processing unit in the personal computer is connected to the input / output device through the bus buffer and the input / output expansion port so that the input / output score can be extended by the central processing unit in the personal computer simulating control signals and addresses. However, the speed of I / O processing is slowed down, and the burden of the central processing unit for I / O scan is naturally increased.

In order to solve the above problems, the microprocessor reads and maintains the data input from the personal computer through the bus buffer, the first-in first-out memory and the bus buffer, and stores the data in the internal memory and the control signal and the input / output device. Input data by sending an address signal, and store the input data in the first-in first-out memory and at the same time store it in the memory of the computer using the direct memory processing (DMA) function and the data stored in the memory of the computer directly By inputting into the first-in first-out memory, the data stored in the first-in first-out memory is output through the buffer according to the order stored in the internal memory, allowing the personal computer to input / output data between the input / output device and the personal computer without interference of the personal computer. It extends beyond the scope and makes it available.

The present invention will be described in detail with reference to the accompanying drawings as follows. 3 is a diagram showing the overall configuration, and receives and interprets an address and control signals from the microprocessor 1 which is in charge of data processing and the microprocessor 1 and the personal computer (PC) while determining the order of operations for input / output scanning. Control logic (2) for determining the direction and opening / closing of the data signals of the bus buffers (6) (7) (8) and the buffer (9), and control the input / output of the data by the control logic (2) (1) an internal memory (3) for executing programs and storing data, a first in first out memory (4) for temporarily expanding data input / output from a personal computer (PC) and an input / output device, and a first-in first-out memory First-in, first-out address control logic 5 for controlling the address of (4), first bus buffer 6, first-in, first-out memory 4, and memory 4 for buffering data and information to and from the personal computer (PC). ) And personal computer (PC) The first bus buffer 6 buffering the output data, the second bus buffer 7 connected thereto, and the third bus buffer buffering data input / output between the microprocessor 1 and the first-in first-out memory 4. (8) and buffers 9 for buffering input / output signals exchanged with the input / output device.

4 illustrates the configuration of the control logic 2 in detail. The microprocessor interface logic 11 receives and transmits various data, addresses, and control signals which are connected to the microprocessor 1 and are processed. 11) The main control logic 12 and the main control logic 12 control the input / output data of the PC and the input / output device to be controlled according to a predetermined control program. Data of the first bus buffer 6 input / output from the personal computer (PC) is controlled to be stored in the first-in, first-out memory 4 via the second bus buffer 7 and the first bus buffer is controlled through the address bus and the control bus, respectively. 6) in accordance with the control signals of the connected bus buffer address control logic 3 and bus buffer control logic 14 and main control logic 12 and stored in the first-in first-out memory 4. Controlled by the microprocessor 1 in accordance with a first-in first-out data flow control logic 15 that controls the first-in, first-out address control logic 5 to determine the address and direction of the data. The memory data control logic 16 to store the input / output data in the internal memory 3 and to interface the data with the input / output device through the buffer 9 and the buffers in the input / output device under the control of the main logic 12. 9) is composed of data input and output control logic 17 for controlling the flow of data input and output through.

Referring to the operating state of the present invention configured as described above are as follows.

First, the data output from the personal computer (PC) is controlled by the control logic (2) into which the control signal and the address signal of the microprocessor (1) are controlled by the first and second bus buffers (6) and (7). The first-in first-out memory 4 is inputted to the first-in first-out memory 4 via the bus buffer 6 and the second bus buffer 7, and the first-in first-out memory 4 is controlled by the address signals of the microprocessor 1 and the control logic 2. The first-in, first-out address control logic 5 inputs the address to the address designated.

The control logic 2 reads and organizes the data inputted into the first-in first-out memory 4 through the third bus buffer 8 according to the data signal of the microprocessor 1, and then stores the data bus in the internal memory 3. The data is input through the microprocessor 1 and stored in the address designated by the microprocessor 1.

Here, the main logic 12 of the control logic 2 into which the address signal, the data signal, and the control signal of the microprocessor 1 are inputted receives the first-in-first-out address control logic 5 through the first-in first-out data flow control logic 15. While controlling, the first and second bus buffers 6 can be determined through the bus buffer address control logic 13 and the bus buffer control logic 14 while determining the address and flow direction of data stored in the first-in, first-out memory 4. (7), the data input from the personal computer (PC) is stored in the designated address of the first-in, first-out memory (4).

The main logic 12 of the control logic 2, which receives an address and a control signal from the microprocessor 1, performs a direct memory access function of a personal computer (PC) on the data stored in the first-in first-out memory (4). Using the second and first bus buffers 7 and 6 to store in a memory (not shown) in the personal computer (PC) and output data stored in the memory in the personal computer (PC) in the same manner. First-in-first-out, controlling first-in first-out address control logic 5 from the microprocessor 1 through address buses via the first and second bus buffers 6 and 7, using a processing (DMA) function. The memory 4 is stored.

At this time, the data output from the personal computer (PC) by the address signals of the control logic (2) and the first-in first-out address control logic (5) receiving the control signal from the microprocessor (1) to the designated address of the first-in, first-out memory (4) Remember

The data stored in this manner is transmitted through the third bus buffer 8 and the buffer 9 by the program execution of the microprocessor 1 and the open / close signal of the program and control logic 2 of the internal memory 3 in which the data is stored. Will be output to the IO device.

On the other hand, it can be seen that the data transferred from the input / output device to the personal computer (PC) is operated in the reverse order.

As described above, in the present invention, the microprocessor 1, the internal memory 3, the control logic 2, and the first-in first-out address control logic 5 exchange data between the personal computer and the input / output device. And input / receive data by automatic input / output scanning by the microprocessor of an input / output scanning device composed of a first-in first-out memory (4) and a plurality of bus buffers (6), (7), (8) and buffers (9). The I / O scan can be processed by itself without interference from the central processing unit, and the burden of the central processing unit in the personal computer can be reduced, thereby improving the efficiency of the central processing unit, and also providing the microprocessor for address and control signals for the input / output unit. (1) By taking charge of this, I / O score can be extended beyond the permissible processing range of the personal computer and the I / O processing speed can be greatly improved. The advantage is that you can provide for.

Claims (1)

An input / output device that scans a state of data input / output between a personal computer (PC) and an input / output device, comprising: a microprocessor (1) for determining the order of operations for input / output scanning and processing of data, and a microprocessor (1) and a personal computer ( Control logic (2) and control logic (2) for determining the direction and opening / closing of data signals of bus buffers (6), (7), (8) and buffer (9) by receiving an address and a control signal from the PC) The input / output of the data is controlled by the internal memory (3) for controlling the program execution and data of the microprocessor (1), and buffering data and information exchanged with the personal computer (PC) under the control of the control logic (2). A first-in, first-out memory 4 for temporarily storing data input and output connected to the first buffer 6 through a first bus buffer 6 and a second buffer 7 controlled by the control logic 2; Under the control of the microprocessor (1) and control logic (2) The first-in first-out address control logic 5 controlling the address of the first-in first-out memory 4 and the data input and output between the first-in first-out memory 4 and the input / output device under the control of the microprocessor 1 or the control logic 2. Perscom input and output scanning device, characterized in that consisting of a third buffer (8) and the buffer (9) for buffering.

Images