JPS61223965A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To attain data transfer with a program transfer instruction time only by operating simultaneously a data reception CPU and a picture processing CPU with the same interruption program and executing transfer instruction between different work RAM areas. CONSTITUTION:The data reception processing CPU 10 and the picture processing CPU 20 are of the same constitution and they are operated by the same clock CLK. The CPUs 10, 20 process data in RAMs 13, 23 according to the program stored in ROMs 12, 22. A reception data fetched in the RAM 13 of the CPU 10 is transferred to the RAM 23 via a data bus D1, a bus control circuit 40 and a data bus D2 by allowing a data transfer control circuit 30 to execute the same interruption program to the CPUs 10, 20 at the same time and the result is displayed on a picture display circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transfer circuit, and more particularly to a data transfer circuit that transfers data between control devices, such as between microprocessors, at high speed. .

[Technical background of the invention and its problems]

Examples of systems that receive data from the outside and display the received data as images include a teletext system and a videotex system. Among these systems, the teletext system transmits data using the horizontal scanning period, which until now was a no-signal portion, within the direct retrace period of the television signal, while the videotex system transmits data using the telephone line. If the transmission speed of these data is slow, a single microprocessor (hereinafter referred to as CPU) can be used to perform reception processing and image processing. However, when the data transmission speed increases, a single CPU may not be able to process the data due to the limitation of the CPU's operating speed. Therefore, it has been considered to use a plurality of CPUs, such as a CPU dedicated to data reception and a CPU dedicated to image processing, to improve the apparent processing power of the CPU. In this case, the CPU that receives data needs to transfer the received data to the CPU that performs image processing.

Next, a conventional data transfer circuit that transfers data between the CPUs described above will be described with reference to the drawings.

In FIG. 7 showing a conventional data transfer circuit, the CPU 7
0 controls the data reception process, CPU Us.

performs image processing control. 71.81 are CPU70 respectively
．． 80 is an oscillator that supplies a reference clock to 80.

CP U3O is based on the clock from the oscillator 71.

The received data received and processed by the data receiving circuit 75 is transferred to the RAM 73 via the data bus according to the program program stored in the ROM 72. Here, the memory space of the CPU 70 is based on the chip enable CEI output from the chip selector 74, Defined by CB2.

The CPU 80 is based on the oscillator 8125-etc.

According to the program stored in ROMB2, RA
The received data stored in M83 is converted into image data. Here again, the memory space of the CPU 5o is the chip enable CE3 output by the chip selector 84.

(Defined by J4. By storing the above image data in the image memory in the image display circuit 85, the image is displayed.

The received data taken into the AM 73 of the CPU 70 is sent to the output port 90. Through the input port 91, the CPU
80 RAM 83. This input/output capo) 9
Data transfer by 0.91K is performed by data transfer control circuit 9.
This is performed under interrupt control by 2.

The above data transfer operation will be explained with reference to the timing chart shown in FIG.

The CPU 70 (FIG. 8a) imports a portion of the received data received through the data receiving circuit 75 into the RAM 73.
When a predetermined amount of data is stored, an output request is issued and the CPUg
If the Q interrupt signal INT (FIG. 8b) is at Ill level, data is output to the output port 9o. At this time, the latch pulse OUT to output capo) 90 (Fig. 8C)
Accordingly, the data transfer control circuit 92 sets the CPU 800 interrupt signal INT to 10 levels, and
The CPU 80 (FIG. 8 d) interrupts the image data processing that has been executed up to that point and starts interrupt processing to collect the amount of data to be transferred. This interrupt processing consists of an interrupt routine that performs interrupt preprocessing, a data input process that takes in transfer data via the input port 91, and a processing process that processes the taken data. Input port 91
Latch pulse IN (8th
Figure e) is also given to the data transfer control circuit 92,
Return the interrupt signal INT to °L° level. Note that the data transfer control circuit 92 can be configured with a set/reset flip-flop.

Furthermore, if transfer data exists in RAM 73, C
The PU 70 issues an output request again, monitors the signal INT to confirm that the CPU 80 has received the data, and then outputs a latch pulse OUT to cause the output port 90 to hold the data. Accordingly, the CPU 80 again receives the transfer data into the A M 83 via the input port 91 by interrupt processing.

In the conventional data transfer circuit described above.

The data length that can be transferred in one interrupt process is limited to the data unit length that can be output to the output port 90. Therefore, if the amount of data to be transferred is large, an interrupt will occur for each data unit. Therefore, as the data transmission speed becomes faster and the amount of data received increases, both the CPU 70 and 80 spend time on data transfer processing, resulting in a situation where data reception processing and image processing cannot be performed sufficiently.

It is also possible to simplify data transfer control by providing a buffer memory such as a FIFO between the CPUs, but depending on the data transmission speed, a large capacity memory is required, which poses problems in terms of circuit scale, cost, etc. There is.

Furthermore, when the CPU 70 attempts to read the data in R and A MB2 and store it in the RAM 73, another set of human power boat and output boat is required, so the circuitry increases to perform bidirectional data transfer. I end up.

[Purpose of the invention]

An object of the present invention is to provide a data transfer circuit that can transfer data between a plurality of control devices at high speed with a small circuit scale.

[Summary of the invention]

In this invention, for example, as shown in FIG. 1, when data is transferred from the CPU 10 side that receives data to the CPU 20 side that performs image processing, the CPU 10 and 20 are configured with the same CPU and are operated with the same clock. . Then, the CPUs 10 and 20 are operated by the same interrupt program at the same time, and the work R set in different memory spaces is executed.
By executing a transfer command between AM areas, data transfer is realized only in the transfer command time of the program.0 [Embodiments of the Invention] The following 1 data transfer circuit of the present invention is used to receive data from the outside. An embodiment in which the received data is applied to a system for displaying images will be described in detail with reference to the drawings.

In FIG. 1 showing the configuration of the embodiment, a CPU 10 controls data reception processing, and a CPU 20 controls image processing. CPUl0 is clock CLK from oscillator 11
Based on the program stored in the ROM 12, the received data received and processed by the data receiving circuit 15 is taken into the RAM 13 via the data bus DI. Here, the memory space of the CPU IQ is defined by chip enables CEx and CB2 from the chip selector 14 that decodes the address bus Al.

The CPU 20 has the same configuration as the CPU 10 described above.

Moreover, they operate with the same clock CLK. This CPU
20 converts the received data stored in the RAM 23 into image data according to the program stored in the R, 0M 22. Here again, the memory space of the CPU 20 is defined by the chip enables CE3 and C84 output by the chip selector U as a love code on the address bus A2. One image is displayed by storing the above image data in the image memory in the image display circuit δ via the data bus D2.

The received data taken into the RAM 13 of the CPUJO is processed by the data transfer control circuit causing both CPUs 10 and 20 to simultaneously execute the same interrupt program.
The data is transferred to the RAM 23 of the CPU 20 via the data bus D1, the bus control circuit 40, and the data bus D2.

The circuit configuration between the data transfer control circuits is shown in Figure 2 in order to cause CPU10 and CPU10 to execute the same interrupt program at the same timing.
Signal OUT 1 indicating data transfer request from Ul0 to 7
It is converted into a signal 0UT2 synchronized with the clock CLK by lip props 31 and 32, and this signal 0UT2 puts the CPU 30 into a hold state. And CPUl
The above-mentioned flip-flop 31 is cleared by the signal lNTl indicating an interrupt request of 0, and the flip-flop okara interrupt signal INT2 is sent to the CPUl0, 20.
and interrupt processing can be started at the same time.

Furthermore, in order to use the data bus D1 of the CPU10 and the data bus D2 of the CPU20 in common during interrupt processing, the bus control circuit KIKU controls the buffers 41 and 42 by the control signal 0°l, respectively, in the read operation as shown in FIG. Control. This control is as shown in Table 1 when the memory space of CPU10.20 is set as shown in FIGS. 4a and 4b, respectively. CPU10 and 2° each perform data reception processing,
In the program ROM area (address n) and work RAM area (address ff1#) for image processing, the data bus D
1. Dz is separated and independent.

On the other hand, during data transfer, in order to cause both CPUs to execute the interrupt program existing in the area at address j on the CPU 10 side, the shipper 41 is activated by the control signal O, and the program code on the data bus Dl is transferred to the data bus. Also supplied on bus D2.

Next, the data transfer operation of the embodiment having the above configuration will be explained with reference to the timing chart of FIG. 5 and the flowchart of FIG. 6.

The CPU 10 (FIG. 5a) takes part of the received data received through the data receiving circuit 15 into the data RAM area at address j of R, A M 13, and issues a transfer request when a predetermined amount of data is stored. . This transfer request starts from step 860 as shown in FIG.
The CPU outputs the signal 0UT2 (Fig. 5C) synchronized with LK.
Since it is applied to the hold terminal [)LI) of 20, CP
After the current machine cycle is completed, U20 relinquishes the right to use the bus and enters a standby state (hold state).
When the interrupt signal is applied, the PU 20 immediately moves to interrupt processing. Period C during which the CPU 20 is in a hold state
The PU 10 waits for a time in step 862, and then outputs an interrupt request signal INTI (FIG. 5d) to the data transfer control circuit in step 863. Interrupt signal INT2 (see FIG. 5, 6) generated from this signal NTl,
Both CPU10. The CPU 20 (Fig. 5 f) is simultaneously K IJ
! A log-in occurs (step 564).

Since this interrupt program exists at address j in the ROM 12, the control signal 0 from the chip selector 14 controls the data buses DI and D2 so that the CPU 20 can read the program code on the data bus Dl. 6th
The interrupt program started at step 870 shown in the figure first performs preparations necessary for interrupt processing at step 871 using an interrupt routine t1. is the signal IN
is output, and the interrupt signal IN'I'2 from the data transfer control circuit (to) is cleared.

The CPU 10, 20 performs the processing. At this time, the bus control circuit 40 K j F) CPU 204 RAM
13 O contents can be imported. Next, in step 873, the received data is processed, for example, the erroneous detection code included in the received data is removed, and then in step 874, the data is written to the address area of R, AMZ (. As described above, no bus control is performed and the data buses DI and D2 are independent. Through the above operations, the data existing in the area at address j of the RAM 13 can be transferred to the address in the RAM 230. Moreover,
This transfer can be realized simply by executing transfer commands of CP'UI0 and CP'UI20.

In order to manage the data transfer amount, the length data stored in the area at address j is read out (step 575), this data is incremented by 1 (step 876), and then stored in the area at address j again (step 577). ).

The above transfer operation is repeated until the length data becomes 0 in step 87g, and then the interrupt processing ends in step 879. Then, the CPUs 10 and 20 return to data reception processing and image processing operations.

(9) If it is necessary to manage the address to which data is transferred, the CPU 1o can also read the data existing at the address in the RAM 23. Similarly to the transfer operation described above, by turning off the bus control circuit to which the control signal I from the chip selector 14 is applied, the data on the data bus D2 is transferred to the data bus D1 when reading the area at the address.
As explained above, in this embodiment, data can be transferred between CPUs 10 and 20 multiple times by '411 interrupt processing only in units of CPU language instructions, so Therefore, a large amount of data can be transferred in a short time, and the efficiency of main processing other than data transfer, such as data reception processing and image processing, is improved. Furthermore, since language instructions exist, the data transfer destination can be specified freely.In addition, since data transfer is performed by sharing a data bus, bidirectional data transfer increases the circuit scale. It also has the advantage of being able to be achieved without having to do so.

In addition, in this embodiment, CPU20 follows CPU10.
However, there were multiple slave CPUs for the main CPU10.
The present invention also provides a C for performing data reception processing and image processing.
It does not apply only between PUs.

[Effects of the Invention] According to the present invention, data can be transferred between a plurality of control devices at high speed, so the data processing efficiency of each control device can be improved. It becomes possible to improve the performance.

Furthermore, it has the advantage that bidirectional data transfer can be performed with a small-scale circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the data transfer circuit of the present invention, FIGS. 2 and 3 are circuit diagrams showing details of each part of the embodiment shown in FIG. 1, and FIG. 4 is a circuit diagram of a CPU. A memory map showing the memory configuration, FIG. 5 a timing chart explaining the operation of the embodiment, and FIG. 6 a flowchart explaining the operation of the embodiment. FIG. 7 is a circuit diagram showing a conventional data transfer circuit, and FIG. 8 is a timing chart explaining the operation of the circuit shown in FIG. 10.20... microprocessor, 12, 22.
...ROM. 13, Z3...RAM. (Capital)...Bus control circuit, Off...Data transfer control circuit. Agent Patent attorney Kensuke Chika (and 1 other person) 4s4 Figure 5 (1, IN' Figure 6 Figure 7 Figure 8 e, IN

Claims (1)

[Claims] A first system in which a data processing operation is defined by a reference clock.
a first memory whose data is accessed via a data bus of the first control device; and a first memory having the same function as the first control device and whose data processing operation is performed by the reference clock. a second control device defined, a second memory to which data is accessed via a data bus of the second control device and set in a memory space different from the first memory; bus control means for bidirectionally switching and controlling the data buses of the first and second control devices; and transfer control means for executing data transfer processing between the first memory and the second memory, and during the transfer processing, the bus control means shares the data bus between the first and second control devices. . A data transfer circuit, wherein the first and second control devices execute data transfer between the first memory and second memory set in mutually different memory spaces.