KR900002812B1 - Frequency discrimination circuit of horizontal synchronous signal - Google Patents
Frequency discrimination circuit of horizontal synchronous signal Download PDFInfo
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- KR900002812B1 KR900002812B1 KR1019860002180A KR860002180A KR900002812B1 KR 900002812 B1 KR900002812 B1 KR 900002812B1 KR 1019860002180 A KR1019860002180 A KR 1019860002180A KR 860002180 A KR860002180 A KR 860002180A KR 900002812 B1 KR900002812 B1 KR 900002812B1
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- horizontal synchronous
- synchronous signal
- operational amplifier
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- 230000001360 synchronised effect Effects 0.000 title claims description 8
- 238000007493 shaping process Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
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- Synchronizing For Television (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 본 발명의 판별호로도.1 is a discrimination diagram of the present invention.
제 2 도는 제 1 도 각부의 파형도2 is a waveform diagram of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 신호정형부 2 : 스위칭부1: signal shaping part 2: switching part
3 : 검출부 4 : 비교부3
5 : 멀티바이브레이터5: Multivibrator
본 발명은 저해상도를 갖는 수평주파수 15KHZ의 영상신호와 고해상도를 갖는 수평주파수 31KHZ의 영상신호를 함께 처리하는 멀티스캔 기능을 가진 텔레비젼 수상기 또는 모니터등에 있어서 입력되는 영상신호의 수평동기 주파수에 따라 내부회로의 동작을 자동으로 절환시킬 수 있는 제어신호를 만드는 수평동기신호의 주파수 판별회로에 관한 것이다.The present invention relates to an internal circuit according to a horizontal synchronization frequency of a video signal input in a television receiver or a monitor having a multi-scan function for processing a video signal having a low resolution horizontal frequency of 15KHZ and a video signal having a high resolution horizontal frequency of 31KHZ together. It relates to a frequency discriminating circuit of a horizontal synchronous signal for making a control signal that can automatically switch the operation.
종래의 멀티스캔 기능을 가진 텔레비젼 수상기 또는 모니터등은 수평동기신호의 주파수를 판별하는 회로가 구성되어 있지 않으므로 사용자는 영상신호의 수평동기 주파수를 미리 조사하고, 그 조사 결과에 따라 멀티스캔 기능의 절환스위치를 수동으로 절한시켜야 되는 결함이 있었다.Since a television receiver or a monitor having a multi-scan function does not have a circuit for discriminating the frequency of a horizontal synchronous signal, the user checks the horizontal synchronous frequency of a video signal in advance and switches the multi-scan function according to the result of the investigation. There was a fault that caused the switch to be manually switched off.
본 발명은 이와같은 종래의 결함을 감안하여, 입력되는 영상신호의 수평동기신호 주파수를 판별하여 31KHZ이면 고전위를 출력하고, 15KHZ이면 저전위를 출력하여 멀티스캔 기능의 절환스위치를 자동으로 절환할 수 있게 창안한 것으로, 이들 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.In view of such a conventional deficiency, the present invention can determine the horizontal synchronous signal frequency of an input video signal and output a high potential at 31 KHZ and a low potential at 15 KHZ to automatically switch the switching switch of the multi-scan function. Invented so as to be described in detail with reference to the accompanying drawings as follows.
제 1 도는 본 발명의 판별회로도로서, 이에 도시한 바와같이 수평동기신호 입력단자(Hi)를 비반전입력단자(+)에 저항(R1)(R2)이 접속된 연산증폭기(OP1)의 반전입력단자(-)에 접속하여 신호정형부(1)를 구성하고, 연산증폭기(OP1)의 출력측은 자힝(R3)을 통해 트랜지스터(TR1)의 베이스에 접속하여 스위칭부(2)를 구성하며 트랜지스터(TR1)의 콜렉터저항(R4) 및 콘덴서(C1)에 접속하여 검출부(3)를 구성함과 아울러 그 접속점을 반전입력단자(-)에 저항 (R5)(R6)이 접속된 연산증폭기(OP2)의 비반전입력단자(+)에 접속하여 비교부(4)를 구성하며, 연산증폭기(OP2)의 출력측은 멀티바이브레이터(5)의 입력층(1N)에 접속하여 구성한 것으로, 도면의 설명중 미설명부호 R7및 C2는 멀티바이브레이터(5)의 시정수를 선정하는 저항 및 콘덴서이고, Vcc는 전원단자이다.FIG. 1 is a discrimination circuit diagram of the present invention. As shown therein, an operational amplifier OP 1 having a horizontal synchronization signal input terminal Hi connected to a non-inverting input terminal + with a resistor R 1 (R 2 ) connected thereto. Is connected to the inverting input terminal (-) of the signal shaping unit 1 , and the output side of the operational amplifier OP 1 is connected to the base of the transistor TR 1 through the magnetizing R 3 to the
이와같이 구성된 본 발명의 작용효과를 상세히 설명하면 다음과 같다.If described in detail the effects of the present invention configured as described above.
전원단자(Vcc)에 전원이 인가되면 그 전원은 저항 (R1)(R2)에 의해 분할되어 연산증폭기(OP1)의 비반전 입력단자(+)에 기준전압을 인가함과 동시에 저항 (R5)(R6)에 의해 분할되어 연산증폭기(OP2)의 반전입력단자(-)에 기준전압을 인가하게 된다.When power is applied to the power supply terminal Vcc, the power is divided by resistors R 1 and R 2 to apply a reference voltage to the non-inverting input terminal (+) of the operational amplifier OP 1 and at the same time, R 5 ) is divided by R 6 to apply a reference voltage to the inverting input terminal (−) of the operational amplifier OP 2 .
이와같은 상태에서 제 2 도의 (a)에서 도시한 바와같이 시간 (t0)에 수평동기신호 입력단자(Hi)로 저해상도의 주파수인 15KHZ의 수평동기신호가 입력되고, 이때, 저항(R1)(R2)에 의해 분할되어 연산증폭기(OP1)의 비반전입력단자(+)에 인가되는 기준전압이 V1이라 가정하면, 연산증폭기(OP1)의 출력측에는 제 2 도의 (b)에 도시한 바와같이 H(여기서, H는 수평동기 기간임)의 주기를 가지는 펄스신호가 출력되고, 그 출력된 펄스신호는 스위칭부(2)의 저항(R3)을 통해 트랜지스터(TR1)의 베이스에 인가되어 그를 온, 오프시키게 되므로 검출부(3)의 콘덴서(C1)에는 제 2 도의 (c)에 도시한 바와같이 트랜지스터(TR1)가 오프될 때 전원단자(VCC)의 전원이 저항(R4)을 통해 충전되고, 트랜지스터(TR1)가 온될 때 콘덴서(C1)에 충전된 전위가 트랜지스터(TR1)를 통해 순식간에 방전되면서 비교부(4)의 연산증폭기)(OP2) 비반전입력단자(+)에 인가된다.In such a state to the second degree (a) one hours (t 0) the horizontal synchronizing signal input terminal (Hi) to as shown in the horizontal synchronizing signal of a low resolution frequency 15KHZ is input, at this time, the resistance (R 1) a (R 2) is divided by the operational amplifier (OP 1), the non-inverting input terminal (+) when the reference voltage is assumed that V 1 is applied to the operational amplifier output, the second degree (b) of (OP 1) of As shown, a pulse signal having a period of H (where H is a horizontal synchronous period) is output, and the output pulse signal of the transistor TR 1 is connected to the resistor R 3 of the
여기서, 저항 (R5)(R6)에 의해 분할되어 연산증폭기(OP2)의 반전입력단자(-)에 인가되는 기준전압(V2)을 상기와 같이 15KHZ의 수평동기신호가 입력될 때 연산증폭기(OP2)의 비반전입력단자(+)에 인가되는 최대 전압보다 약간 낮게 설정하면, 연산증폭기(OP2)의 출력후에는 제 2 도의 (d)에 도시한 바와같이 펄스신호가 출력되어 멀티바이브레이터(5)의 입력단자(IN)에 인가되므로 멀티바이브레이터(5)의 출력단자()에는 시간 (t1)에 제 2 도의 (e)에 도시한 바와같이 저 전위가 출력되고, 여기서, 저항(R7) 및 콘덴서(C2)의 시정수가 1H 이상이 되게 그 값을 설정하면, 멀티바이브레이터(5)의 출력단자()에 고전위가 출력되기 전에 그의 입력단자(IN)로 펄스신호가 입력되므로 멀티바이브레이터(5)의 출력단자()에는 계속 저전위가 출력된다.Here, when the horizontal synchronization signal of 15 KHZ is inputted to the reference voltage V 2 divided by the resistor R 5 (R 6 ) and applied to the inverting input terminal (−) of the operational amplifier OP 2 as described above. When a bit is set lower than the maximum voltage applied to the non-inverting input terminal (+) of the operational amplifier (OP 2), after the output of the operational amplifier (OP 2) is a pulse signal output as shown in the second degree (d) Is applied to the input terminal IN of the
그리고 제 2 도의 (a)에 도시한 바와같이 시간 (t2)에 고해상도의 주파수인 31KHZ의 수평동기신호가 입력되면 연산증폭기(OP1)의 출력측에는 제 2 도의 (b)에 도시한 바와같이 ½H의 주기로 펄스신호가 출력되어 트랜지스터(TR1)는 ½H의 주기로 온, 오프를 반복하므로 제 2 도의 (c)에 도시한 바와같이 콘덴서(C1)에 충전 및 방전되면서 연산증폭기(OP2)의 비반전입력단자(+)에 인가되는 저압이 연산증폭기(OP2)의 반전입력단자(-)에 인가되는 기준전압(V2) 보다 낮게된다.As shown in (a) of FIG. 2 , when the horizontal synchronization signal of 31 KHZ, which is a high resolution frequency, is input at the time t 2 , the output side of the operational amplifier OP 1 is shown in FIG. Since the pulse signal is output in a cycle of ½H and the transistor TR 1 is repeatedly turned on and off in a cycle of ½H, the operational amplifier OP 2 is charged and discharged in the capacitor C 1 as shown in FIG. The low voltage applied to the non-inverting input terminal (+) of is lower than the reference voltage (V 2 ) applied to the inverting input terminal (−) of the operational amplifier OP 2 .
따라서 제 2 도의 (d)에 도시한 바와같이 연산증폭기(OP2)의 출력측에는 계속 저전위가 출력되므로 멀티바이브레이터(5)의 출력단자()에는 제2도의 (e)에 도시한 바와같이 저항(R7) 및 콘덴서(C2)에 의해 설정된 일정시간 (t3)부터 계속 고전위를 출력하게 된다.Therefore, as shown in (d) of FIG. 2 , since the low potential is continuously output to the output side of the operational amplifier OP 2 , the output terminal of the multivibrator 5 ( ), The high potential is continuously output from the predetermined time t 3 set by the resistor R 7 and the capacitor C 2 as shown in FIG.
이상에서 설명한 바와같이 본 발명은 수평동기주파수가 저해상도인 15KHZ이면 저전위를 출력하고, 고해상도인 31KHZ이면 고전위를 출력하므로 멀티스캔 기능을 가진 텔레비젼 수상기 또는 모니터등의 수평동기 주파수에 따른 내부회로를 자동으로 제어할 수 있는 효과가 있다.As described above, the present invention outputs a low potential when the horizontal synchronization frequency is low resolution 15KHZ, and outputs a high potential when the high resolution 31KHZ is high. Therefore, an internal circuit according to the horizontal synchronization frequency of a television receiver or a monitor having a multi-scan function is provided. There is an effect that can be controlled automatically.
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Application Number | Priority Date | Filing Date | Title |
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KR1019860002180A KR900002812B1 (en) | 1986-03-24 | 1986-03-24 | Frequency discrimination circuit of horizontal synchronous signal |
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Application Number | Priority Date | Filing Date | Title |
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KR1019860002180A KR900002812B1 (en) | 1986-03-24 | 1986-03-24 | Frequency discrimination circuit of horizontal synchronous signal |
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KR870009578A KR870009578A (en) | 1987-10-27 |
KR900002812B1 true KR900002812B1 (en) | 1990-04-30 |
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KR1019860002180A KR900002812B1 (en) | 1986-03-24 | 1986-03-24 | Frequency discrimination circuit of horizontal synchronous signal |
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