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KR900002562A - 인버터회로 및 그 회로를 이용한 쵸퍼형 비교기회로 - Google Patents

인버터회로 및 그 회로를 이용한 쵸퍼형 비교기회로 Download PDF

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Publication number
KR900002562A
KR900002562A KR1019890009470A KR890009470A KR900002562A KR 900002562 A KR900002562 A KR 900002562A KR 1019890009470 A KR1019890009470 A KR 1019890009470A KR 890009470 A KR890009470 A KR 890009470A KR 900002562 A KR900002562 A KR 900002562A
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KR
South Korea
Prior art keywords
fet
input
circuit
power supply
inverter circuit
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Application number
KR1019890009470A
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English (en)
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KR920004342B1 (ko
Inventor
히데오 사카이
도모다카 사이토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR900002562A publication Critical patent/KR900002562A/ko
Application granted granted Critical
Publication of KR920004342B1 publication Critical patent/KR920004342B1/ko
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

인버터회로 및 그 회로를 이용한 쵸퍼형 비교기회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1 실시예를 나타낸 회로도.
제 2 도는 본 발명의 다른 실시예를 나타낸 회로도.

Claims (2)

  1. 제 1 도전형 제 1 절연게이트 전계효과트랜지스터(Q1: 제 1 IG-FET)와, 제 2도전형 제 2 절연게이트 전계효과트랜지스터(Q2: WP 2 IG-FET), 상기 제 1 IG-FET(Q1)의 소오스전극에 접속되는 제 1 전원(VSS), 상기 제 2 IG-FET(Q2)의 소오스전극에 접속되는 제 2 전원(VDD)을 구비하여 구성되면서, 상기 제 1 IG-FET(Q1)의 채널길이(LN)와 채널폭(WN), 제 2 IG-FET(Q2)의 채널길이(LP)와 채널폭(WP), 상기 제 1 전원의 배선저항값(RS), 제 2 전원 배선저항값(RD), 제 1 IG-FET(Q1)의 캐리어의 이동도(㎲), 제 2 IG-FET(Q2)의 캐리어 이동도(μP)간에
    의 관계가 근사적으로 성립되도록 하고, 공통접속된 상기 제 2 IG-FET(Q1,Q2)의 게이트적극을 입력으로 하며, 공통 접속된 제 1, 제 2 IG-FET(Q1,Q2)의 드레인전극을 출력으로 하도록 된것을 특징으로 하는 인버터회로.
  2. 제 1 도전형 제 1 절전연게이트 전계효과트랜지스터 (Q1; 제1 IG-FET)와, 제 2 도형 제 2 절연게이트 전계효과트랜지스터(Q2; 제2 IG-FET), 상기 제1 IG-FET(Q1) 의 소오스전극에 접속되는 제 1 전원(VSS), 상기제2 IG-FET(Q2)의 소오스전극에 접속되는 제 2 전원(VDD)을 구비하여 구성되면서, 상기 제1 IG-FET(Q1)의 채널길이 (LN)와 채널폭(WN), 제2 IG-FET(Q2)의 채널길이(LP)와 채널폭(WP), 상기 제 1 전원의 배선저항값(RS), 제 2 전원의 배선저항값(RD), 제1 IG-FET(Q1)의 캐리어의 이동도 (㎲), 제2 IG-FET(Q2)의 캐리어의 이동도(μP)간에
    의 관계가 근사적으로 성립되도록 하고, 공통접속된 상기 제1, 제2 제2 IG-FET(Q1,Q2)의 게이트전극을 입력으로 하며, 공통 접속된 제1, 제 2 IG-FET(Q1,Q2)의 드레인전극을 출력으로 하도록 된 인버터회로(3)와 ; 이 인버터회로(3)의 입,출력단 사이에 설치되어 비교입력이 샘플링시와 비교입력 및 기준전압의 비교시에 각각 대응되게 상기 입,출력단 사이를 개폐시키는 스위치수단(Q3,Q4)을 구비하여 상기 인버터회로(3)의 입력부에 기준전압과 비교입력의 차에 따른 전압을 입력시키도록 된 것을 특징으로 하는 쵸퍼형 비교기회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890009470A 1988-07-04 1989-07-04 인버터회로 및 그 회로를 이용한 쵸퍼형 비교기회로 Expired KR920004342B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16641088 1988-07-04
JP88-166410 1988-07-04

Publications (2)

Publication Number Publication Date
KR900002562A true KR900002562A (ko) 1990-02-28
KR920004342B1 KR920004342B1 (ko) 1992-06-01

Family

ID=15830904

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890009470A Expired KR920004342B1 (ko) 1988-07-04 1989-07-04 인버터회로 및 그 회로를 이용한 쵸퍼형 비교기회로

Country Status (5)

Country Link
US (1) US5041744A (ko)
EP (1) EP0349981B1 (ko)
JP (1) JPH02124624A (ko)
KR (1) KR920004342B1 (ko)
DE (1) DE68920785T2 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04266217A (ja) * 1991-02-21 1992-09-22 Matsushita Electric Ind Co Ltd 入力バッファ回路
JP2894004B2 (ja) * 1991-06-13 1999-05-24 松下電器産業株式会社 周波数変換回路
US6320427B1 (en) * 2000-10-11 2001-11-20 Winbond Electronics Corp. High-speed, low-power continuous-time CMOS current comparator
JP4255733B2 (ja) * 2003-04-09 2009-04-15 ソニー株式会社 コンパレータ、差動増幅器、２段増幅器及びアナログ／ディジタル変換器
KR100589376B1 (ko) 2003-11-27 2006-06-14 삼성에스디아이 주식회사 역다중화기를 이용한 발광 표시 장치
JP5186818B2 (ja) * 2007-06-22 2013-04-24 ミツミ電機株式会社 チョッパ型コンパレータ
KR101408857B1 (ko) * 2014-03-31 2014-06-19 김영준 벨크로 전사 라벨의 제조방법 및 이에 의해 제조된 벨크로 전사 라벨

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58170213A (ja) * 1982-03-31 1983-10-06 Toshiba Corp 電圧比較回路
US4547683A (en) * 1982-10-18 1985-10-15 Intersil, Inc. High speed charge balancing comparator
JPH07117559B2 (ja) * 1986-03-29 1995-12-18 株式会社東芝 電圧比較回路

Also Published As

Publication number Publication date
EP0349981A3 (en) 1990-06-20
JPH02124624A (ja) 1990-05-11
EP0349981B1 (en) 1995-01-25
KR920004342B1 (ko) 1992-06-01
DE68920785T2 (de) 1995-06-29
DE68920785D1 (de) 1995-03-09
EP0349981A2 (en) 1990-01-10
US5041744A (en) 1991-08-20

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