KR900000021Y1 - Circuit for processing specific characters of monitor - Google Patents
Circuit for processing specific characters of monitor Download PDFInfo
- Publication number
- KR900000021Y1 KR900000021Y1 KR2019870002715U KR870002715U KR900000021Y1 KR 900000021 Y1 KR900000021 Y1 KR 900000021Y1 KR 2019870002715 U KR2019870002715 U KR 2019870002715U KR 870002715 U KR870002715 U KR 870002715U KR 900000021 Y1 KR900000021 Y1 KR 900000021Y1
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- KR
- South Korea
- Prior art keywords
- character
- terminal
- monitor
- shift register
- signal generator
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/222—Control of the character-code memory
- G09G5/225—Control of the character-code memory comprising a loadable character generator
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안 특징 문자 처리회로도1 is a character processing circuit diagram of the subject innovation
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
CG : 문자 신호 발생기 Video-RAM : 비디오 램CG: Text Signal Generator Video-RAM: Video RAM
CC : 문자 코드 Raster-Add : 라스터어드레스CC: Character Code Raster-Add: Raster Address
Add : 어드레스단자 Shift-R : 쉬프트 레지스터Add: Address terminal Shift-R: Shift register
D0-D7: 출력단자 I0-I7: 입력단자D 0 -D 7 : Output terminal I 0 -I 7 : Input terminal
NAND : 낸드게이트 D-FF : 디플립플롭NAND: NANDGATE D-FF: Deflip Flop
DS0: 쉬프트 레지스터 입력단자DS 0 : Shift register input terminal
본 고안은 모니터의 특정 문자 처리회로에 관한 것이다.The present invention relates to a specific character processing circuit of a monitor.
일반적으로 문자 도르셀의 표준은 이 도트로서 보통의 문자발생기(Character generater)요컨대 알파벳트등과 같은 문자들은 8비트로서 디스플레이가 가능하지만 라인 긋는 것과 같은 특정문자는 회로를 변경하여야만 가능토록 되어 있다.In general, the character Dolcell standard is this dot, so that characters such as normal character generators, such as alphabets, can be displayed as 8 bits, but specific characters such as line drawing are required only by changing circuits.
즉 문자신호 발생기의 데이타비트는 8비트로서 회로적으로 직접 가능한 데이타는 8게만으로 가능하지만 9도트의 데이타를 처리하기 위하여는 외부조직이 부가되어야 한다.That is, the data bit of the character signal generator is 8 bits, and only 8 data can be directly circuited, but an external organization must be added to process 9 dots of data.
만약 라인 긋는 것과 같은 특정문자를 8도트로서 사용한다면 화면전체에 라인을 그을때 라인이 끊어져 보이게 된다.If you use 8 dots for a specific character, such as drawing a line, the line will be broken when you draw the line across the screen.
그러므로 종래의 회로에서는 속성 제어기의 내부에 9∼10도르의 데이타 입력이 허용되어 직접 연결하여 사용하면 되지만 데이타 입력이 8도트인 쉬프트레지스터를 사용한 경우에는 외부조직이 부가되어야 한다.Therefore, in the conventional circuit, data inputs of 9 to 10 degrees are allowed inside the attribute controller, so that they can be directly connected. However, when a shift register having 8 dots of data input is used, an external structure must be added.
따라서 본 고안의 목적은 데이타 입력이 8도트린 쉬프트레지스터에 낸드게이트 및 플립플롭을 연결하여 9비트도트의 라인을 긋을수 있게 함으로써 속성제어기를 사용하는 것보다 저렴한 가격으로 특정 문자를 처리할수 있게 한 것이다.Therefore, the purpose of the present invention is to enable the data input to connect NAND gate and flip-flop to the 8-dot shift register so that 9-bit dots can be drawn to process specific characters at a lower price than using the property controller. It is.
이하 첨두된 도면에 의하여 본 고안을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
비디오램(Video-RAM)으로 부터 출려되는 문자코드다자(CC)및 CRTC로 부터 출력되는 라스터어드레스(Raster Add)의 데이타를 받아 문자로 변환시키는 문자 신호 발생기(CG)의 출력단자(D0∼D7)는 모니터에 연결된 쉬프트레지스터(Shlft-R)의 입력단자(I0∼I7)에 각각 연결하되 상기 비디오 램(Video-RAM)의 문자코드(CC)단자와 문자신호 발생기(CG)의 출력단자(D0)는 넨드게이트(NAND)의 입력단자에 연결하고 그 낸드게이트(NAND)의 출력단자는 디플립플롭(D-FF)의 입력단자(D)에 연결하며 디플립플롭(D-FF)의 출력단자(Q)는 상기 쉬프트 레지스터(Shift-R)의 입력(DS0)에 연결하여 된 것으로 도면중 미설명 부호 CP는 도트주파수 발생기(DFG)로 부터 도트 클럭을 받는 클럭단자이다.Output terminal (D 0 ) of character signal generator (CG) which receives character code data (CC) issued from video-RAM and raster add data output from CRTC and converts them into characters. D- 7 ) are connected to the input terminals I 0 to I 7 of the shift register (Shlft-R) connected to the monitor, respectively, and the character code (CC) terminal and the character signal generator (CG) of the video RAM. ) Output terminal (D 0 ) is connected to the input terminal of the NAND gate, and the output terminal of the NAND gate (NAND) is connected to the input terminal (D) of the flip-flop (D-FF) and the flip-flop ( The output terminal Q of D-FF is connected to the input DS 0 of the shift register Shift-R. In the drawing, reference numeral CP denotes a clock that receives a dot clock from a dot frequency generator (DFG). It is a terminal.
이상에서와 같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.
먼저 부호를 문자 패턴의 신호로 변환하는 문자 신호 발생기(CG)의 어드레스단자(Add)에는 비디오 램(Video-RAM)으로 부터 출력되는 문자 코드 데이타(CC)밋 CRTC로 부터 출력되는 라스터어드레스(Raster Add)데이타를 받아 부호를 문자패턴의 신호로 변환하여 문자 신호발생기(CG)의 출력단자(D0~D7)를 통하여 쉬프트레지스터 (Shift-R)의 입력단자(I0~I7)에 입력시키면 쉬프트레지스터(Shift-R)에서는 이 신호를 모니터(Moniter)에 디스플레이하게 되는데 이때 낸드게이트(NAND)의 입력단자에는 비디오램(Video-RAM)으로 부터 출력되는 문자코드(CC)데이타와 문자신호발생기(CG)의 최하위비트인 출력단자(D0)가 모두 "1"이 입력되면 낸드게이트(NAND)의 출력 단자는 "0"이 출력되고 이 출력신호는 디플립플롭(D-FF)의 입력단자(D)에 인가되면서 디플립플롭(D-FF)의 클럭단자에 인가되는 비디오의 도트클록신호(Dot Clock)에 의하여 한 주기 동안 지연되어 쉬프트레지스터(Shift-R)의 입력단자(DS0)에는 "0"을 입력시키게 된다.First, the address terminal (Add) of the character signal generator (CG) which converts a sign into a signal of a character pattern is provided with a raster address outputted from a character code data (CC) mid CRTC outputted from a video RAM. Raster Add) receives the data and converts the sign into the signal of the character pattern and inputs the shift register (Shift-R) through the output terminals (D 0 ~ D 7 ) of the character signal generator (CG) (I 0 ~ I 7 ). When input to, Shift-R displays this signal on monitor. At this time, NAND gate's input terminal has character code (CC) data output from Video-RAM and When the output terminal D 0 , which is the least significant bit of the character signal generator CG, is inputted with "1", the output terminal of the NAND gate is outputted with "0", and this output signal is a flip-flop (D-FF). Is applied to the clock terminal of the deflip-flop (D-FF) while being applied to the input terminal (D) of Is thereby, enter a "0" input terminals (DS 0) of the video dot clock signal (Dot Clock) is delayed for one cycle shift register (Shift-R) by.
따라서 쉬프트레지스터(Shift-R)에서는 그 자체 특성에 의하여 최상위 비트인 입력단자(In)에 "1"이 세트된다.Therefore, in the shift register Shift-R, "1" is set to the input terminal In, which is the most significant bit, by its own characteristics.
이 세트된 신호를 해당하는 문자에 라인을 그어 모니터(Moniter)에 디스플레이 시키게 되는 것이다.This set signal is displayed on the monitor by drawing a line on the corresponding character.
이상에서 설명한 바와 같이 본 고안은 문자 신호 발생기로 부터 출력되는 데이타를 직접 속성제어기에 연결하여 사용하지 않고 8도트인 쉬프트 레지스터를 사용하되 이에 낸드게이트 및 디플립플롭을 연결하여 9비트의 도트라인을 그을수 있게 함으로써 저렴한 가격의 특정문자처리회로를 제공해줄수 있는 이점이 있는 것이다.As described above, the present invention uses a shift register of 8 dots instead of directly connecting the data output from the character signal generator to the property controller, but uses a NAND gate and a flip-flop to connect a 9-bit dot line. By doing so, there is an advantage to provide a low-cost specific character processing circuit.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870002715U KR900000021Y1 (en) | 1987-03-04 | 1987-03-04 | Circuit for processing specific characters of monitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870002715U KR900000021Y1 (en) | 1987-03-04 | 1987-03-04 | Circuit for processing specific characters of monitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR880018747U KR880018747U (en) | 1988-10-29 |
| KR900000021Y1 true KR900000021Y1 (en) | 1990-01-30 |
Family
ID=19260261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870002715U Expired KR900000021Y1 (en) | 1987-03-04 | 1987-03-04 | Circuit for processing specific characters of monitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR900000021Y1 (en) |
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1987
- 1987-03-04 KR KR2019870002715U patent/KR900000021Y1/en not_active Expired
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| Publication number | Publication date |
|---|---|
| KR880018747U (en) | 1988-10-29 |
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