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KR890005859A - 집적회로 칩 조립품 - Google Patents

집적회로 칩 조립품 Download PDF

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Publication number
KR890005859A
KR890005859A KR1019880012469A KR880012469A KR890005859A KR 890005859 A KR890005859 A KR 890005859A KR 1019880012469 A KR1019880012469 A KR 1019880012469A KR 880012469 A KR880012469 A KR 880012469A KR 890005859 A KR890005859 A KR 890005859A
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KR
South Korea
Prior art keywords
integrated circuit
circuit chip
chip assembly
assembly
contact portion
Prior art date
Application number
KR1019880012469A
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English (en)
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KR920003437B1 (ko
Inventor
닐 페이퍼 로렌
유휀윙
Original Assignee
오레그 이.앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR890005859A publication Critical patent/KR890005859A/ko
Application granted granted Critical
Publication of KR920003437B1 publication Critical patent/KR920003437B1/ko

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
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    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Weting (AREA)

Abstract

내용 없음

Description

집적회로 칩 조립품
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 양호한 실시예에 따르는 에치된 정렬 특징을 갖는 집적회로 칩의 개략도.
제2도는 제1도 칩의 개략적인 단면도.
제3도는 본 발명의 양호한 실시예에 따르는 정렬 특징을 갖는 캐리어 기판의 단면도.
* 도면의 주요부분에 대한 부호의 설명
11 : 집적회로 칩 12, 32 : 땜납 패드
13 : 함몰부 33 : 피라미드

Claims (7)

  1. 기판 및 집적회로 칩을 구비하는 조립품에 있어서, 여기서 제1표면으로 지정된 상기 칩의 표면은 제2표면으로 지정된 상기 기판 표면의 대응부분과 대향되며, 상기 제1표면은 제1접촉부를 포함하며 상기 제2표면은 제2접촉부를 포함하며, 상기 조립품은 상기 제1접촉부와 제2접촉부 사이의 소정의 거리를 교차하여 전기 상호 접속시키는 장치를 구비하며, 적어도 상기 제1 또는 제2표면은 대향표면과 물리적인 접촉하는 표면 특징을 포함하는 것을 특징으로 하는 집적회로 칩 조립품.
  2. 제1항에 있어서, 상기 전기 상호접속장치는 땜납을 포함하는 것을 특징으로 하는 집적회로 칩 조립품.
  3. 제1항에 있어서, 상기 표면 특징은 상기 대향 표면상의 대응하는 표면 특징과 접촉하는 것을 특징으로 하는 집적회로 칩 조립품.
  4. 제3항에 있어서, 상기 표면 특징은 거의 매팅 표면 특징인 것을 특징으로 하는 집적회로 칩 조립품.
  5. 제1항에 있어서, 상기 기판과 상기 칩은 거의 단결점 실리콘으로 구성하는 것을 특징으로 하는 집적회로 칩 조립품.
  6. 제5항에 있어서, 상기 제1표면과 상기 제2표면은 거의(100)-표면인 것을 특징으로 하는 집적회로 칩 조립품.
  7. 제6항에 있어서, 상기 표면 특징은 거의 피라미드형인 것을 특징으로 하는 집적회로 칩 조립품.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880012469A 1987-09-30 1988-09-27 집적회로 칩 조립품 KR920003437B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10297787A 1987-09-30 1987-09-30
US102,977 1987-09-30

Publications (2)

Publication Number Publication Date
KR890005859A true KR890005859A (ko) 1989-05-17
KR920003437B1 KR920003437B1 (ko) 1992-05-01

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KR1019880012469A KR920003437B1 (ko) 1987-09-30 1988-09-27 집적회로 칩 조립품

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EP (1) EP0312217A1 (ko)
JP (1) JPH01109757A (ko)
KR (1) KR920003437B1 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4020048A1 (de) * 1990-06-23 1992-01-02 Ant Nachrichtentech Anordnung aus substrat und bauelement und verfahren zur herstellung
JPH0770806B2 (ja) * 1990-08-22 1995-07-31 株式会社エーユーイー研究所 超音波溶着による電子回路およびその製造方法
DE4242565C1 (de) * 1992-12-16 1994-03-17 Deutsche Aerospace Verfahren zur Justage von Halbleiterscheiben zueinander
DE69405832T2 (de) * 1993-07-28 1998-02-05 Whitaker Corp Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür
US5657207A (en) * 1995-03-24 1997-08-12 Packard Hughes Interconnect Company Alignment means for integrated circuit chips
DE19750073A1 (de) * 1997-11-12 1999-05-20 Bosch Gmbh Robert Schaltungsträgerplatte
EP1122567A1 (en) * 2000-02-02 2001-08-08 Corning Incorporated Passive alignement using slanted wall pedestal
JP4407785B2 (ja) * 2000-10-24 2010-02-03 ソニー株式会社 半導体装置及びその検査方法
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US8063650B2 (en) 2002-11-27 2011-11-22 Rambus Inc. Testing fuse configurations in semiconductor devices
US7701045B2 (en) 2006-04-11 2010-04-20 Rambus Inc. Point-to-point connection topology for stacked devices
US9899312B2 (en) 2006-04-13 2018-02-20 Rambus Inc. Isolating electric paths in semiconductor device packages
US7768847B2 (en) 2008-04-09 2010-08-03 Rambus Inc. Programmable memory repair scheme
US9153508B2 (en) 2011-08-17 2015-10-06 Rambus Inc. Multi-chip package and interposer with signal line compression
US9570196B2 (en) 2011-09-01 2017-02-14 Rambus Inc. Testing through-silicon-vias

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920633B2 (ja) * 1980-05-20 1984-05-14 新日本製鐵株式会社 鋳造用ノズル
JPS5920633U (ja) * 1982-07-30 1984-02-08 富士通株式会社 バンプ接合型半導体装置

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JPH01109757A (ja) 1989-04-26
JPH0519307B2 (ko) 1993-03-16
EP0312217A1 (en) 1989-04-19
KR920003437B1 (ko) 1992-05-01

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