KR890005844A - 매입 유전체상에 형성된 배선층 및 그 제조방법 - Google Patents
매입 유전체상에 형성된 배선층 및 그 제조방법Info
- Publication number
- KR890005844A KR890005844A KR1019880003697A KR880003697A KR890005844A KR 890005844 A KR890005844 A KR 890005844A KR 1019880003697 A KR1019880003697 A KR 1019880003697A KR 880003697 A KR880003697 A KR 880003697A KR 890005844 A KR890005844 A KR 890005844A
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- layer formed
- wiring layer
- embedded dielectric
- dielectric
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63255747A JPH01175554A (ja) | 1987-12-30 | 1988-10-11 | 自動車の制御装置 |
| US07/292,557 US4925252A (en) | 1987-12-30 | 1988-12-30 | Automobile brake system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62225039A JPS6467945A (en) | 1987-09-08 | 1987-09-08 | Wiring layer formed on buried dielectric and manufacture thereof |
| JP62-225039 | 1987-09-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890005844A true KR890005844A (ko) | 1989-05-17 |
| KR940008358B1 KR940008358B1 (ko) | 1994-09-12 |
Family
ID=16823091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019880003697A KR940008358B1 (ko) | 1987-09-08 | 1988-04-01 | 매입 유전체상에 형성된 배선층 및 그 제조방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5041898A (ko) |
| JP (1) | JPS6467945A (ko) |
| KR (1) | KR940008358B1 (ko) |
| DE (2) | DE3825547A1 (ko) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5516720A (en) * | 1994-02-14 | 1996-05-14 | United Microelectronics Corporation | Stress relaxation in dielectric before metallization |
| KR100236097B1 (ko) * | 1996-10-30 | 1999-12-15 | 김영환 | 반도체 장치의 격리막 형성방법 |
| US6306727B1 (en) | 1997-08-18 | 2001-10-23 | Micron Technology, Inc. | Advanced isolation process for large memory arrays |
| US6451655B1 (en) * | 1999-08-26 | 2002-09-17 | Stmicroelectronics S.R.L. | Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimension |
| DE10041691A1 (de) | 2000-08-24 | 2002-03-14 | Infineon Technologies Ag | Halbleiteranordnung |
| DE10051909B4 (de) * | 2000-10-19 | 2007-03-22 | Infineon Technologies Ag | Randabschluss für Hochvolt-Halbleiterbauelement und Verfahren zum Herstellen eines Isolationstrenches in einem Halbleiterkörper für solchen Randabschluss |
| DE10242661A1 (de) * | 2002-09-13 | 2004-03-25 | Conti Temic Microelectronic Gmbh | Verfahren zum Herstellen von Isolationsstrukturen |
| US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
| US7247570B2 (en) * | 2004-08-19 | 2007-07-24 | Micron Technology, Inc. | Silicon pillars for vertical transistors |
| US7285812B2 (en) * | 2004-09-02 | 2007-10-23 | Micron Technology, Inc. | Vertical transistors |
| US7199419B2 (en) * | 2004-12-13 | 2007-04-03 | Micron Technology, Inc. | Memory structure for reduced floating body effect |
| US7229895B2 (en) * | 2005-01-14 | 2007-06-12 | Micron Technology, Inc | Memory array buried digit line |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
| US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
| US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
| KR100703042B1 (ko) * | 2006-09-08 | 2007-04-09 | (주)에이펙스 | 검사용 프로브 기판 및 그 제조 방법 |
| KR100703043B1 (ko) * | 2006-09-21 | 2007-04-09 | (주)에이펙스 | 검사용 프로브 기판 및 그 제조 방법 |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| IT1397603B1 (it) * | 2009-12-21 | 2013-01-16 | St Microelectronics Srl | Trincee di isolamento per strati semiconduttori. |
| US9401363B2 (en) | 2011-08-23 | 2016-07-26 | Micron Technology, Inc. | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2949360A1 (de) * | 1978-12-08 | 1980-06-26 | Hitachi Ltd | Verfahren zur herstellung einer oxidierten isolation fuer integrierte schaltungen |
| JPS56146247A (en) * | 1980-03-25 | 1981-11-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58105551A (ja) * | 1981-11-20 | 1983-06-23 | Fujitsu Ltd | 半導体装置 |
| JPS58200554A (ja) * | 1982-05-19 | 1983-11-22 | Hitachi Ltd | 半導体装置の製造方法 |
| US4502913A (en) * | 1982-06-30 | 1985-03-05 | International Business Machines Corporation | Total dielectric isolation for integrated circuits |
| US4819054A (en) * | 1982-09-29 | 1989-04-04 | Hitachi, Ltd. | Semiconductor IC with dual groove isolation |
| US4910575A (en) * | 1986-06-16 | 1990-03-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and its manufacturing method |
-
1987
- 1987-09-08 JP JP62225039A patent/JPS6467945A/ja active Pending
-
1988
- 1988-04-01 KR KR1019880003697A patent/KR940008358B1/ko not_active IP Right Cessation
- 1988-07-27 DE DE3825547A patent/DE3825547A1/de active Granted
- 1988-07-27 DE DE19883844719 patent/DE3844719C2/de not_active Expired - Lifetime
- 1988-08-11 US US07/231,064 patent/US5041898A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3844719C2 (de) | 1995-06-14 |
| KR940008358B1 (ko) | 1994-09-12 |
| DE3825547A1 (de) | 1989-03-16 |
| JPS6467945A (en) | 1989-03-14 |
| DE3825547C2 (ko) | 1992-12-03 |
| US5041898A (en) | 1991-08-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19880401 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19880401 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19910730 Patent event code: PE09021S01D |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 19920206 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 19910730 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |
|
| J2X1 | Appeal (before the patent court) |
Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL |
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| PJ2001 | Appeal |
Appeal kind category: Appeal against decision to decline refusal Decision date: 19940228 Appeal identifier: 1992201000888 Request date: 19920507 |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19920715 Patent event code: PE09021S01D |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19940309 Patent event code: PE09021S01D |
|
| G160 | Decision to publish patent application | ||
| PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19940819 |
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| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19941210 |
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| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19941214 Patent event code: PR07011E01D |
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| PR1002 | Payment of registration fee |
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| PR1001 | Payment of annual fee |
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| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |