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KR890005617A - Device controlling access to video memory - Google Patents

Device controlling access to video memory Download PDF

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Publication number
KR890005617A
KR890005617A KR1019880011051A KR880011051A KR890005617A KR 890005617 A KR890005617 A KR 890005617A KR 1019880011051 A KR1019880011051 A KR 1019880011051A KR 880011051 A KR880011051 A KR 880011051A KR 890005617 A KR890005617 A KR 890005617A
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KR
South Korea
Prior art keywords
video memory
video
video data
memory
buffer
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Application number
KR1019880011051A
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Korean (ko)
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KR960009839B1 (en
Inventor
기미오 야마무라
Original Assignee
고오도 유우시
가부시끼가이샤 허드슨
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Publication of KR890005617A publication Critical patent/KR890005617A/en
Application granted granted Critical
Publication of KR960009839B1 publication Critical patent/KR960009839B1/en
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음No content

Description

비디오메모리의 액세스를 제어하는 장치Device controlling access to video memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따라 비디오메모리의 액세스를 제어하는 장치가 포함되는 스크린상에 영상을 표시하는 장치를 표시하는 블럭도.1 is a block diagram showing a device for displaying an image on a screen including a device for controlling access to a video memory according to the present invention.

제2도 (A)는 VRAM에 비디오신호 기록과 거기에서 비디오신호의 판독제어를 위한 비디오 표시제어를 표시하는 블럭도.Fig. 2A is a block diagram showing video display control for recording a video signal in a VRAM and reading control of the video signal therefrom.

제2도 (B)는 제 1도의 장치에서 스크린 상에 스프라이트(sprite)를 표시하는 장치를 표시하는 블럭도.FIG. 2B is a block diagram showing an apparatus for displaying a sprite on a screen in the apparatus of FIG.

Claims (5)

비디오메모리의 액세스를 위해 도트폭의 내용을 가지고 있는 레지스터수단, 상기 레지스터수단의 상기 내용에 따라 상기 도트폭을 결정하는 수단, 상기 도트폭에 따라 결정되는 타이밍에서 상기 비디오 메모리를 어드레싱하는 수단, 상기 타이밍에서 상기 비디오 메모리로부터 판독되는 비디오데이타를 래칭하는 수단과 스크린상에 상기 비디오 데이터가 표시됨으로서 확정되는 패턴으로 구성되는 것을 특징으로 하는 비디오 메모리의 액세스를 제어하는 장치.Register means having contents of a dot width for access to a video memory, means for determining the dot width in accordance with the contents of the register means, means for addressing the video memory at a timing determined in accordance with the dot width, Means for latching video data read from the video memory at timing and a pattern determined by displaying the video data on a screen. 제 1 항에 있어서, 상기 비디오 데이터가 상기 비디오 메모리의 문자생성기에서 판독되고 그리고 상기 문자생성기가 상기 비디오 메모리에 포함된 백그라운드 어트리뷰트 테이블에 기억된 분자코드에 따라 어드레스되는 것으로 구성된 것을 특징으로 하는 비디오 메모리 액세스를 제어하는 장치.2. The video memory according to claim 1, wherein the video data is read from a character generator of the video memory and the character generator is addressed according to a molecular code stored in a background attribute table included in the video memory. Device that controls access. 제 2 항에 있어서 상기 문자생성기가 상기 패턴을 확정하기 위해 결합된 4명을 포함하는 것으로 구성되는 것을 특징으로 하는 비디오 메모리의 액세스를 제어하는 장치.3. The apparatus of claim 2, wherein the character generator comprises four persons combined to determine the pattern. 제 2 항에 있어서 상기 비디오 메모리의 표시사이클 동안에 상기 비디오 메모리에서 판독되는 상기 비디오 데이타를 기억하는 버퍼수단, 상기 비디오 메모리의 표시사이클이 종료될때까지 기억되는 상기 비디오데이터로 더욱 구성되는 것을 특징으로 하는 비디오메모리의 액세스를 제어하는 장치.3. The display apparatus according to claim 2, further comprising buffer means for storing the video data read out of the video memory during the display cycle of the video memory, and the video data stored until the display cycle of the video memory ends. Device for controlling access to video memory. 소정의 타이밍에서 비디오메모리를 어드레싱하는 수단, 상기 비디오메모리에 기록되고 그리고 상기 비디오메모리에서 판독되는 비디오데이타를 기억하는 버퍼수단, 상기 비디오데이타를 기억하기 위해 상기 버퍼수단을 제어하는 수단, 그중의 상기 비디오데이타가 상기 비디오 메모기가 상기 비디오메모리의 표시자사이클중에 어드레스될 때 상기 버퍼수단에 기억되고 상기 비디오 메모리의 상기 표시사이클이 종료될때 상기 버퍼에서 전송되는 것으로 구성된 것을 특징으로 하는 비디오메모리의 액세스를 제어하는 장치.Means for addressing a video memory at a predetermined timing, buffer means for storing video data recorded in and read out of the video memory, means for controlling the buffer means for storing the video data, wherein the Video data is stored in the buffer means when the video memo is addressed during an indicator cycle of the video memory and transmitted from the buffer when the display cycle of the video memory ends. Controlling device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR88011051A 1987-09-19 1988-08-30 Apparatus for controlling access of video memory Expired - Lifetime KR960009839B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-235483 1987-09-19
JP62235483A JP2610275B2 (en) 1987-09-19 1987-09-19 Video memory transfer controller

Publications (2)

Publication Number Publication Date
KR890005617A true KR890005617A (en) 1989-05-16
KR960009839B1 KR960009839B1 (en) 1996-07-24

Family

ID=16986729

Family Applications (1)

Application Number Title Priority Date Filing Date
KR88011051A Expired - Lifetime KR960009839B1 (en) 1987-09-19 1988-08-30 Apparatus for controlling access of video memory

Country Status (3)

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JP (1) JP2610275B2 (en)
KR (1) KR960009839B1 (en)
GB (1) GB2210238B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2065979C (en) * 1991-06-10 1999-01-19 Stephen Patrick Thompson Mode dependent minimum fifo fill level controls processor access to video memory
JPH05158655A (en) * 1991-12-05 1993-06-25 Fujitsu Ltd Clock transfer circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59143190A (en) * 1983-02-05 1984-08-16 富士通株式会社 Information processor
JPS61163021A (en) * 1985-01-14 1986-07-23 Mitsubishi Heavy Ind Ltd Noise control device of automobile

Also Published As

Publication number Publication date
GB8818787D0 (en) 1988-09-07
JP2610275B2 (en) 1997-05-14
KR960009839B1 (en) 1996-07-24
GB2210238A (en) 1989-06-01
JPS6478319A (en) 1989-03-23
GB2210238B (en) 1992-05-13

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