KR880011656A - 레지스터 회로 - Google Patents
레지스터 회로 Download PDFInfo
- Publication number
- KR880011656A KR880011656A KR1019880002806A KR880002806A KR880011656A KR 880011656 A KR880011656 A KR 880011656A KR 1019880002806 A KR1019880002806 A KR 1019880002806A KR 880002806 A KR880002806 A KR 880002806A KR 880011656 A KR880011656 A KR 880011656A
- Authority
- KR
- South Korea
- Prior art keywords
- data signal
- signal
- storage means
- receiving
- input terminal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Static Random-Access Memory (AREA)
- Communication Control (AREA)
Abstract
Description
Claims (4)
- 데이터 신호와 선택 신호를 각각 공통으로 수신하며 각각이 데이터 신호 수신용 제1입력단자를 포함하는 다수의 레지스터, 선택신호에 대응하는 1신호를 수신하는 제2입력단자, 기억된 데이터 신호를 출력하는 출력단자, 상기 출력 단자에 연결되어 데이터 신호를 기억하는 기억수단, 및 선택 신호가 유효할 때 데이터 신호를 기억수단에 전송하고, 데이타 신호가 이미 상기 기억수단에 기억되며, 선택신호가 무효일 때 상기 기억수단을 리세팅하기 위해 상기 기억수단 상기 제1입력단자, 상기 제2입력단자, 및 상기 출력단자에 접속된 제어수단으로 구성되는 것을 특징으로 하는 레지스터 회로.
- 제1항에 있어서, 상기 제어수단은 데이터 신호와 대응 선택 신호를 수신하는 제1NAND게이트. 기억된 데이터 신호와 데이터 신호의 반전신호를 수신하는 제2NAND게이트, 및 제1 및 제2 NAND게이트의 출력을 수신하며 상기 기억수단에 연결된 제3NAND게이트로 구성되는 것을 특징으로 하는 레지스터 회로.
- 제1항에 있어서, 상기 기억수단이 상기 제어수단에 연결된 플립플롭과, 소정상태로 플립플롭을 초기에 세팅하기 위한 수단으로 구성되는 것을 특징으로 하는 레지스터 회로.
- 제1항에 있어서, 상기 레지스터 회로가 다수의 데이터 신호를 수신하며, 상기 레지스터들이 다수의 그룹으로 나누어지고, 그리고 각각의 상기 그룹이 데이타 신호의 대응 1신호를 수신하는 것을 특징으로 하는 레지스터 회로.※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6016287A JPH0827725B2 (ja) | 1987-03-17 | 1987-03-17 | レジスタ回路 |
JP62-60162 | 1987-03-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880011656A true KR880011656A (ko) | 1988-10-29 |
KR920003699B1 KR920003699B1 (ko) | 1992-05-09 |
Family
ID=13134181
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880002806A KR920003699B1 (ko) | 1987-03-17 | 1988-03-17 | 레지스터회로 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4866742A (ko) |
EP (1) | EP0283230B1 (ko) |
JP (1) | JPH0827725B2 (ko) |
KR (1) | KR920003699B1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313420A (en) * | 1987-04-24 | 1994-05-17 | Kabushiki Kaisha Toshiba | Programmable semiconductor memory |
DE3855180T2 (de) * | 1988-10-24 | 1996-10-02 | Toshiba Kawasaki Kk | Programmierbarer Halbleiterspeicher |
US5125011A (en) * | 1990-02-13 | 1992-06-23 | Chips & Technologies, Inc. | Apparatus for masking data bits |
JPH04100150A (ja) * | 1990-08-20 | 1992-04-02 | Fujitsu Ltd | レジスタ回路 |
US5166960A (en) * | 1992-04-20 | 1992-11-24 | Xerox Corporation | Parallel multi-phased a-Si shift register for fast addressing of an a-Si array |
US5903283A (en) * | 1997-08-27 | 1999-05-11 | Chips & Technologies, Inc. | Video memory controller with dynamic bus arbitration |
JP5027435B2 (ja) * | 2006-03-31 | 2012-09-19 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3274555A (en) * | 1962-02-26 | 1966-09-20 | Sperry Rand Corp | Digital data transfer circuit utilizing tunnel diodes |
DE1487826B2 (de) * | 1966-05-21 | 1972-02-24 | Siemens AG, 1000 Berlin u. 8000 München | Schaltungsanordnung zur prioritaetsgerechten datenuebertragung |
DE2041149A1 (de) * | 1969-12-02 | 1971-06-16 | Elektro App Werke Berlin Trept | Vorrangschaltung |
JPS51148307A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | Speech path network control system |
US4045693A (en) * | 1976-07-08 | 1977-08-30 | Gte Automatic Electric Laboratories Incorporated | Negative r-s triggered latch |
JPS5935453B2 (ja) * | 1976-11-30 | 1984-08-29 | 日本電気株式会社 | 割込優先順位決定回路 |
DE2848803A1 (de) * | 1978-11-10 | 1980-05-22 | Bosch Gmbh Robert | Schaltungsanordnung zur uebertragung eines digitalen datensignals |
JPS56159742A (en) * | 1980-05-13 | 1981-12-09 | Nec Corp | Priority level controller |
US4419762A (en) * | 1982-02-08 | 1983-12-06 | Sperry Corporation | Asynchronous status register |
JPS59142626A (ja) * | 1983-02-01 | 1984-08-15 | Nec Corp | バス競合防止回路 |
JPS619748A (ja) * | 1984-06-25 | 1986-01-17 | Nec Corp | 入出力制御装置 |
DE3477072D1 (en) * | 1984-09-05 | 1989-04-13 | Siemens Ag | Arrangement for priority allocation |
-
1987
- 1987-03-17 JP JP6016287A patent/JPH0827725B2/ja not_active Expired - Fee Related
-
1988
- 1988-03-04 US US07/164,287 patent/US4866742A/en not_active Expired - Lifetime
- 1988-03-14 EP EP88302202A patent/EP0283230B1/en not_active Expired - Lifetime
- 1988-03-17 KR KR1019880002806A patent/KR920003699B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH0827725B2 (ja) | 1996-03-21 |
JPS63226735A (ja) | 1988-09-21 |
KR920003699B1 (ko) | 1992-05-09 |
US4866742A (en) | 1989-09-12 |
EP0283230A3 (en) | 1990-07-04 |
EP0283230B1 (en) | 1994-07-27 |
EP0283230A2 (en) | 1988-09-21 |
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