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KR880006789A - High Reliability Semiconductor Device and Manufacturing Method Thereof - Google Patents

High Reliability Semiconductor Device and Manufacturing Method Thereof Download PDF

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Publication number
KR880006789A
KR880006789A KR870012658A KR870012658A KR880006789A KR 880006789 A KR880006789 A KR 880006789A KR 870012658 A KR870012658 A KR 870012658A KR 870012658 A KR870012658 A KR 870012658A KR 880006789 A KR880006789 A KR 880006789A
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gate electrode
region
semiconductor device
gate
concentration region
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KR870012658A
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Korean (ko)
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KR900008153B1 (en
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류우이지 이자와
에이지 다게다
야스오 이구라
아게미 하마다
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미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

고신뢰성 반도체 장치와 그 제조 방법High Reliability Semiconductor Device and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 게이트/드레인의 오버랩량과 가로방향 전계 강도와의 관계를 도시하는 도면.1 is a diagram showing the relationship between the overlap amount of the gate / drain and the lateral electric field strength.

제2도는 게이트/드레인의 오버랩량과 최대 전계 강도의 발생점의 위치와의 관계를 도시하는 도면.2 is a diagram showing the relationship between the overlap amount of the gate / drain and the position of the generation point of the maximum field strength.

제3도는 본 발명의 제1의 실시예의 MOS 트랜지스터의 단면도.3 is a cross-sectional view of the MOS transistor of the first embodiment of the present invention.

제4도는(a)~(c)는 본 발명의 제2의 실시예의 제조 공정을 도시하는 단면도(A)-(c) is sectional drawing which shows the manufacturing process of 2nd Example of this invention.

제5도는 본 발명의 제3의 실시예를 도시하는 단면도.5 is a sectional view showing a third embodiment of the present invention.

제6도는 본 발명의 제4의 실시예를 도시하는 단면도.6 is a sectional view showing a fourth embodiment of the present invention.

제8도는 본 발명의 제6의 실시예를 도시하는 단면도.8 is a sectional view showing a sixth embodiment of the present invention.

제9도는 본 발명의 제7의 실시예를 도시하는 단면도.9 is a sectional view showing a seventh embodiment of the present invention.

제10도는 본 발명의 제8의 실시예를 도시하는 단면도.10 is a sectional view showing an eighth embodiment of the present invention.

제11도 (a), (b)는 본 발명의 제9의 실시예를 도시하는 단면도.11 (a) and 11 (b) are cross-sectional views showing the ninth embodiment of the present invention.

제12도는 본 발명의 제10의 실시예를 도시하는 단면도.12 is a sectional view showing a tenth embodiment of the present invention.

제13도 (a), (b)는 본 발명의 제11의 실시예의 제조 공정을 도시하는 단면도.13 (a) and 13 (b) are sectional views showing the manufacturing process of the eleventh embodiment of the present invention.

Claims (14)

반도체 기판, 상기 반도체 기판상에 마련된 게이트 절연막, 상기 게이트 절연막을 거쳐서 마련된 게이트 전극 및 상기 게이트 전극의 양측의 상기 반도체 기판의 표면영역에 마련되어 저농도 영역과 고농도 영역을 가지며 저농도 영역은 고농도 영역보다 상기 게이트 전극측에 마련된 소오스 및 드레인 영역을 가지고, 상기 소오스, 드레인 영역의 공핍화 영역 중 적어도 상기 게이트 절연막과 접촉하는 영역이 상기 게이트 전극에 의해서 덮어져 있는 것을 특징으로 하는 반도체 장치.A semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided through the gate insulating film, and a surface region of the semiconductor substrate on both sides of the gate electrode, and having a low concentration region and a high concentration region, wherein the low concentration region has the gate rather than the high concentration region. And a source and drain region provided on an electrode side, wherein at least a region in contact with said gate insulating film of said depletion region of said source and drain region is covered by said gate electrode. 특허청구의 범위 제1항에 있어서, 상기 게이트 전극은 제1의 게이트 전극과 상기 제1의 게이트 전극의 측부에 전기적으로 접속된 제2의 게이트 전극을 갖는 반도체 장치.The semiconductor device according to claim 1, wherein the gate electrode has a first gate electrode and a second gate electrode electrically connected to a side portion of the first gate electrode. 특허청구의 범위 제2항에 있어서, 상기 제1의 게이트 전극은 상기 저농도 영역상까지 신장해서 마련되고, 상기 제2의 게이트 전극은 상기 고농도 영역상까지 신장해서 마련되어 있는 반도체 장치.The semiconductor device according to claim 2, wherein the first gate electrode extends to the low concentration region, and the second gate electrode extends to the high concentration region. 특허청구의 범위 제1항에 있어서, 상기 고농도 영역은 상기 저농도 영역보다 낮은 부분에 마련되어 있는 반도체 장치.The semiconductor device according to claim 1, wherein the high concentration region is provided at a portion lower than the low concentration region. 특허청구의 범위 제2항에 있어서, 상기 제2의 게이트 전극의 밑에는 상기 제1의 게이트전극이 신장하고 있는 반도체 장치.The semiconductor device according to claim 2, wherein the first gate electrode extends under the second gate electrode. 특허청구의 범위 제2항에 있어서, 상기 저농도 영역은 상기 고농도 영역을 덮도록 마련되어 있는 반도체 장치.The semiconductor device according to claim 2, wherein the low concentration region covers the high concentration region. 반도체 기판, 상기 반도체 기판상에 마련된 게이트 절연막, 상기 게이트 절연막을 거쳐서 마련된 게이트 전극 및 상기 게이트 전극의 양측의 상기 반도체 기판의 표면영역에 마련되어 저농도 영역과 고농도 영역을 가지며 저농도 영역은 고농도 영역보다 상기 게이트 전극측에 마련된 소오스 및 드레인 영역을 가지고, 상기 게이트 전극은 제1의 게이트 전극과 상기 제1의 게이트 전극의 측부에 전기적으로 접속된 제2의 게이트 전극을 가지며 상기 제2의 게이트 전극의 측벽부에 스페이서 영역을 갖는 반도체 장치.A semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a gate electrode provided through the gate insulating film, and a surface region of the semiconductor substrate on both sides of the gate electrode, and having a low concentration region and a high concentration region, wherein the low concentration region has the gate rather than the high concentration region. A source and drain region provided on an electrode side, wherein the gate electrode has a first gate electrode and a second gate electrode electrically connected to a side of the first gate electrode, and has a sidewall portion of the second gate electrode. A semiconductor device having a spacer region on the. 특허청구의 범위 제7항에 있어서, 상기 소오스, 드레인 영역의 공핍화 영역중 적어도 상기 게이트 절연막과 접속하는 영역이 상기 게이트 전극에 의해서 덮어져 있는 반도체 장치.8. The semiconductor device according to claim 7, wherein at least a region connected to the gate insulating film among the depletion regions of the source and drain regions is covered by the gate electrode. 특허청구의 범위 제8항에 있어서, 상기 제1의 게이트 전극은 상기 저농도 영역상까지 신장해서 마련되며 상기 제2의 게이트 전극은 상기 고농도 영역상까지 신장해서 마련되어 있는 반도체 장치.The semiconductor device according to claim 8, wherein the first gate electrode extends to the low concentration region, and the second gate electrode extends to the high concentration region. 반도체 기판상에 절연막을 거쳐서 제1의 게이트 전극을 형성하는 공정과, 상기 제1의 게이트 전극의 측벽에 제2의 게이트 전극을 형성하는 공정과, 상기 게이트 전극의 양측의 상기 반도체 기판의 표면 영역에 불순물을 도프해서 소오스, 드레인 영역을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.Forming a first gate electrode on the semiconductor substrate via an insulating film, forming a second gate electrode on the sidewall of the first gate electrode, and a surface region of the semiconductor substrate on both sides of the gate electrode And a step of forming a source and a drain region by doping an impurity in the semiconductor device. 특허청구의 범위 제10항에 있어서, 상기 제2의 게이트 전극을 형성하는데에는 상기 전극 형성용의 도전성막을 전체면에 퇴적한 후, 이방성 에칭을 행하는 것에 의해 상기 제1의 게이트 전극의 측벽에 상기 제2의 게이트 전극을 남아 있게 해서 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method according to claim 10, wherein the second gate electrode is formed by depositing the conductive film for forming the electrode on the entire surface and then performing anisotropic etching on the sidewalls of the first gate electrode. A method of manufacturing a semiconductor device, characterized in that the second gate electrode remains. 특허청구의 범위 제 10항에 있어서 제2의 게이트 전극의 측벽에 CVD법 또는 열 산화법을 사용해서 절연막을 형성하는 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조방법.11. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of forming an insulating film on the sidewall of the second gate electrode by using a CVD method or a thermal oxidation method. 특허청구의 범위 제10항에 있어서, 상기 제1의 게티트 전극을 막두께의 두꺼운 부분과 얇은 부분으로 구성하며, 상기 제1의 게이트 전극의 얇은 부분의 상부에서 또한 두꺼운 부분의 측벽에 제2의 게이트 전극을 마련한 것을 특징으로 한는 반도체 장치의 제조방법.12. The device of claim 10, wherein the first gett electrode comprises a thick portion and a thin portion of a film thickness, and includes a second portion on a sidewall of the thick portion and on top of the thin portion of the first gate electrode. A method for manufacturing a semiconductor device, comprising providing a gate electrode. 특허청구의 범위 제10항에 있어서, 상기 제1의 게이트 전극을 마스크로 하는 불순물 도프에 의해 저농도 소오스, 드레인 영역을 형성한 후, 상기 제2의 게이트 전극을 형성하고 다음에 상기 제2의 게이트 전극의 측벽에 절연막을 형성하여 상기 절연막을 마스크로 하는 불순물 도프에 의해 고농도 소오스, 드레인 영역을 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method according to claim 10, wherein after forming a low concentration source and a drain region by impurity doping using the first gate electrode as a mask, the second gate electrode is formed, and then the second gate is formed. A method for manufacturing a semiconductor device, comprising forming an insulating film on a sidewall of an electrode to form a high concentration source and drain region by impurity doping using the insulating film as a mask. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870012658A 1986-11-11 1987-11-10 High Reliability Semiconductor Device and Manufacturing Method Thereof Expired KR900008153B1 (en)

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Application Number Priority Date Filing Date Title
JP61266543A JPS63122174A (en) 1986-11-11 1986-11-11 Semiconductor device and its manufacturing method
JP61-266543 1986-11-11

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KR880006789A true KR880006789A (en) 1988-07-25
KR900008153B1 KR900008153B1 (en) 1990-11-03

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Publication number Priority date Publication date Assignee Title
JPH0212835A (en) * 1988-06-30 1990-01-17 Toshiba Corp Semiconductor device and its manufacturing method
US5141891A (en) * 1988-11-09 1992-08-25 Mitsubishi Denki Kabushiki Kaisha MIS-type semiconductor device of LDD structure and manufacturing method thereof
JPH0334550A (en) * 1989-06-30 1991-02-14 Nec Corp Mos transistor
JP2995838B2 (en) * 1990-01-11 1999-12-27 セイコーエプソン株式会社 Mis type semiconductor device and manufacture thereof
US5798550A (en) * 1990-10-01 1998-08-25 Nippondenso Co. Ltd. Vertical type semiconductor device and gate structure
US5426327A (en) * 1990-10-05 1995-06-20 Nippon Steel Corporation MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations
JPH0629524A (en) * 1992-04-14 1994-02-04 Toshiba Corp Manufacture of semiconductor device
US5654212A (en) * 1995-06-30 1997-08-05 Winbond Electronics Corp. Method for making a variable length LDD spacer structure
KR100995330B1 (en) * 2003-04-29 2010-11-19 매그나칩 반도체 유한회사 Manufacturing method of semiconductor device
JP2007311498A (en) * 2006-05-17 2007-11-29 Denso Corp Semiconductor device
JP5332781B2 (en) * 2009-03-19 2013-11-06 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device

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JPS63122174A (en) 1988-05-26

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