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KR880006771A - 알루미늄 또는 알루미늄 화하물로 구성된 적어도 2개의 도체층을 포함하는 반도체 집적회로 및 그 제조방법 - Google Patents

알루미늄 또는 알루미늄 화하물로 구성된 적어도 2개의 도체층을 포함하는 반도체 집적회로 및 그 제조방법 Download PDF

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KR880006771A
KR880006771A KR870013476A KR870013476A KR880006771A KR 880006771 A KR880006771 A KR 880006771A KR 870013476 A KR870013476 A KR 870013476A KR 870013476 A KR870013476 A KR 870013476A KR 880006771 A KR880006771 A KR 880006771A
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titanium
tungsten
integrated circuit
aluminum
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KR910007108B1 (ko
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퀘허 페터
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휘티쉬.네테부쉬
지멘스 악티엔게젤샤프트
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Abstract

내용 없음

Description

알루미늄 또는 알루미늄 화합물로 구성된 적어도 2개의 도체층을 포함하는 반도체 집적회로 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 공정에서 제1의 단계를 나타내는 반도체기판의 횡단면도.
제2도는 본 발명의 공정중 제2의 단계를 보이기위한 기판의 횡단면도.
제3도는 본 발명의 공정에서 또다른 단계를 나타내기 위한 기판의 횡단면도.

Claims (25)

  1. 절연층에 의해 분리되고 알루미늄 또는 알루미늄 화합물로 구성된 적어도 2개의 도체층과 실리콘으로 구성된 기판을 포함하고, 상기 도체층이 서로 연결되거나 금속 실리사이드로된 중간층 및 텅스텐으로된 콘택홀 필러에 의해 접촉되어질 실리콘기판내 및 기판위 영역과 연결되는 반도체 집적회로에 있어서, 접촉되어질 실리콘영역에 비례하여 텅스텐 실리사이드(WSix), 티타늄/텅스텐, 티타늄/질화텅스텐 및 질화텅스텐으로 구성된 그룹으로부터 선택된 제1의 금속중간층과, 덮개층으로서 각각의 도체층 위에 배치되는 또 하나의 금속 실리사이드로된 중간층과, 그리고 금속공정을 위한 핵형성층으로서 도체층 밑에 배치되고, 알루미늄의 전자이동저항을 증진시키기 위한 각각의 중간층을 포함하는 것을 특징으로 하는 반도체 집적회로.
  2. 제1항에 있어서, 덮개층은 몰리브덴 실리사이드(MoSi2)로 구송되는 것을 특징으로 하는 반도체 집적회로.
  3. 제1항에 있어서, 핵형성층은 티타늄/질화티타늄의 2중층으로 구성되는 것을 특징으로 하는 반도체 집적회로.
  4. 제2항에 있어서, 핵형성층이 티타늄/질화티타늄의 2중층으로 구성되는 것을 특징으로 하는 반도체 집적회로.
  5. 제3항에 있어서, 2중층은 약 10내지 30nm 두께의 티타늄층과 약 50 내지 150nm 두께의 질화티타늄으로 구성되는 것을 특징으로 하는 반도체 집적회로.
  6. 제4항에 있어서, 2중층이 약 10 내지 30nm 두께의 티타늄층과 약 50 내지 150nm 두께의 질화티타늄으로 구성되는 것을 특징으로 하는 반도체 집적회로.
  7. 제1항에 있어서, 덮개층은 약 50 내지 200nm 두께를 가진 몰리브덴 실리사이드로부터 구성되는 것을 특징으로 하는 반도체 집적회로.
  8. 제5항에 있어서, 덮개층이 약 50 내지 200nm의 두께를 가진 몰리브덴 실리사이드로부터 구성되는 것을 특징으로 하는 반도체 집적회로.
  9. 제1항에 있어서, 제1의 중간층은 약 5 내지 30nm의 두께를 갖는 것을 특징으로 하는 반도체 집적회로.
  10. 제8항에 있어서, 제1의 중간층이 약 5 내지 30nm의 두께를 갖는 것을 특징으로 하는 반도체 집적회로.
  11. 제1항에 있어서, 콘택홀에서의 장벽 및 핵형성층은 티타늄/텅스텐, 티타늄/텅스텐/질화물을 기상성장 또는 티타늄/질화물을 음극 스퍼터링하여 피착되는 텅스텐 실리사이드로 형성되는 것을 특징으로 하는 반도체 집적회로.
  12. 제1항에 있어서, 덮개층은 몰리브덴 실리사이드로부터 구성되고, 핵형성층은 티타늄/티타늄 질화믈로부터 구성되며, 이 모두는 음극 스퍼링에 의해 생성되는 것을 특징으로 하는 반도체 집적회로.
  13. 제1항에 있어서, 도체층은 알루미늄, 알루미늄/실리콘, 알루미늄/구리, 알루미늄/구리/실리콘 및 알루미늄/실리콘/티타늄으로 구성된 그룹으로부터 선택된 화합물로부터 구성되고 음극 스퍼터링 또는 기상성장에 의해 생성되는 것을 특징으로 하는 반도체 집적회로.
  14. 적어도 2개의 도체층으로 구성되는 다층구조를 갖는 기판을 포함하는 반도체 집적회로의 제작방법에 있어서, a) 텅스텐 실리사이드, 티타늄/텅스텐, 티타늄/질화텅스텐 또는 질화티타늄으로 구성된 그룹으로부터 선택된 화합물로된 핵형성 및 장벽층을 가지고 제1의 절연층내에 있는 비아홀을 갖는 반도체기판 전체표면에 걸쳐 코팅한 다음, 저압 기상성장(LPCVD)법에 의해 텅스텐으로 비아홀을 메꾸고, b) 비아홀이 다만 텅스텐으로 채워져 있기까지 기판의 표면에서 텅스텐/텅스텐 실리사이드층을 제거하고, c) 먼저 티타늄층을 전체표면에 걸쳐 성장시킨 다음 기상성장 및/또는 음극 스퍼터링으로 질화티타늄을 성장시키며, d) 기상성장 또는 음극 스퍼터링에 의해 알루미늄 또는 알루미늄 화합물로된 제1의 도체층을 인가하고, e) 음극 스퍼터링으로 제1의 도체층에 몰리브덴 실리사이드로 구성된 덮개층을 입히고, f) 제1의 도체층에 몰리브덴 실리사이드로된 덮개층과 티타늄/질화티타늄의 부속층을 구조화시키고, g) 제2의 절연층을 성장시키고나서 그 안으로 비아홀을 유도하고, h) 6불화텅스텐을 채택한 기상성장에 의한 텅스텐의 선택적인 성장으로 비아홀을 텅스텐으로 메꾸고, i) 상기 단계 (c)에서의 방법으로 티타늄/질화티타늄으로 구성된 또 하나의 층을 성장시키고, 그리고, j) 알루미늄 또는 알루미늄합금으로된 제2의 금속층과 몰리브덴 실리사이드로된 덮개층을 상기 단계(d) 및 (e)에서의 방법으로 생성시키는 단계로 이루어진 집적회로의 제작방법.
  15. 제14항에 있어서, 처리단계들이 다음과 같은 층두께를 갖는 집적회로를 생성하도록 실행되는 것을 특징으로 하는 집접회로의 제작방법 : 텅스텐 실리사이드층(WSix)이 대략 5 내지 30nm : 티타늄층(Ti)이 약 10 내지 30nm : 질화티타늄층(TiN)이 약 50 내지 150nm : 몰리브덴 실리사이드층(MoSi2)이 약 100nm.
  16. 제14항에 있어서, 도체층 사이의 절연층이 SiOx로 구성되고, 음극 스퍼터링에 의해 생성되는 것을 특징으로 하는 집적회로의 제작방법.
  17. 제14항에 있어서, 처리단계가 다수의 도체층에 대해 임의의 회수로 반복되는 것을 특징으로 하는 집적회로의 제작방법.
  18. 제14항의 방법에 따른 제품.
  19. 제17항의 방법에 따른 제품.
  20. 적어도 2개의 도체층으로 구성되는 다층구조를 갖는 기판을 포함하는 반도체 집적회로의 제작방법에 있어서, a) 반도체기판의 제1의 절연층내의 비아홀내로 기상의 선택적인 성장에 의해 텅스텐 실리사이드, 티타늄/텅스텐, 티타늄/질화텅스텐, 질화티타늄으로 구성된 그룹으로부터 선택된 화합물을 성장시킨 다음 저압의 화학적 가상성장법에 의해 비아홀을 텅스텐으로 메꾸고, b) 먼저 티타늄층을 전체표면에 걸쳐 성장시키고, 그 다음 기상성장 및/또는 음극 스퍼터링에 의해 질화티타늄층을 성장시키고, c) 기상성장 또는 음극 스퍼터링에 의해 알루미늄 또는 알루미늄 화합물로된 제1의 도체층을 가하고, d) 음극 스퍼터링에 의해 몰리브덴 실리사이드로 구성된 덮개층을 제1의 도체층 위에 가하고, e) 몰리브덴 실리사이드로된 덮개층과 티타늄/질화티타늄으로된 부수층과 함께 제1의 도체층을 구조화시키고, f) 제2의 절연층을 성장시킨 다음 그 안으로 비아홀을 형성하고, g) 6불화텅스텐을 채택한 기상으로부터의 텅스텐의 선택적인 성장에 의해 비아홀을 텅스텐으로 메꾸고, h) 상기 단계 (b)의 방법으로 티타늄/질화티타늄으로 구성된 또 하나의 층을 성장시키고, i) 알루미늄 또는 알루미늄 화합물로된 제2의 금속층과 몰리브덴 실리사이드로된 덮개층을 상기 단계(c) 및 (d)의 방법으로 생성시키는 단계로 이루어진 것을 특징으로 하는 집적회로의 제작방법.
  21. 제20항에 있어서, 처리단계들이 다음과 같은 층두께를 갖는 집적회로를 생성하도록 실행되는 것을 특징으로 하는 집적회로의 제작방법 : 텅스텐 실리사이드층(WSix)이 대략 5 내지 30nm ; 티타늄(Ti)이 약 10 내지 30nm ; 질화티타늄층(TiN)이 약 50 내지 150nm ; 몰리브덴 실리사이드층(MoSi2)이 약 100nm.
  22. 제20항에 있어서, 도체층 사이의 절연층이 SiOx로 구성되고 그 절연층은 음극 스퍼링으로 생성되는 것을 특징으로 하는 반도체 집적회로의 제작방법.
  23. 제20항에 있어서, 처리단계가 다수의 도체층에 대해 임의의 회수로 반복되는 것을 특징으로 하는 집적회로의 제작방법.
  24. 제20항의 방법에 따른 제품.
  25. 제23항의 방법에 따른 제품.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870013476A 1986-11-28 1987-11-28 알루미늄 또는 알루미늄 화합물로 구성된 적어도 2개의 도체층을 포함하는 반도체 집적회로 및 그 제조방법 KR910007108B1 (ko)

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