KR830001978B1 - Power amplification circuit - Google Patents

Abstract

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Description

Power amplification circuit

1 is a circuit diagram showing an embodiment of the power amplifier circuit according to the present invention.

2 (a) and 2 (b) are explanatory diagrams for explaining the operation of the embodiment.

3 is a circuit diagram showing another embodiment of the present invention.

4 is a characteristic diagram for explaining the operation of a circuit obtained by partially modifying the circuit shown in FIG.

5 is a circuit configuration diagram showing a modification of the present invention.

The present invention relates, in particular, to improvements in power amplifier circuits well suited for integrated circuit (IC) ization.

In general, a power amplifier circuit uses a semi-complementary single-ended push-pull (SEPP) amplifier circuit at its output stage when integrated circuit (IC) is used.

However, due to the integrated circuit (IC), a large current PNP transistor is difficult to manufacture, and in particular, a lateral (multi-collector) PNP transistor has a small current capacity and a small current amplification rate. Low gain bandwidth (fr) has problems such as being easy to oscillate and has a drawback that it is difficult to obtain large output.

In addition, when the transistor of the output terminal connected to the complimentary terminal is an emitter ground type, the output amplification can be large even without a bootstrap circuit. There was an unreasonable point of becoming difficult.

Therefore, it is considered that the output terminal of the power amplification circuit is made of only the same polarity, that is, the NPN transistor, compared with the conventional one, but setting the idle current is also difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to easily set the idle current, obtain a large output, and also operate stably and reliably, and very good power amplification suitable for integrated circuit (IC). It is an object to provide a circuit.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In FIG. 1, reference numeral 11 denotes an input terminal supplied with a power amplified signal, for example, a jack or the like, the outer terminal 111 of which is grounded, and an inner terminal 112. ) Is connected to the base of a PNP transistor Q ₁ via a capacitor C ₁ . The connection point between the capacitor C ₁ and the base of the transistor Q ₁ is grounded via a resistor R ₁ . Further, the connection point of the emitter and the emitter and the transistor (Q ₂₎ for being connected to the emitter of the emitter of PNP type transistor (Q ₂₎ of said one transistor (Q _1), the transistor (Q ₁₎ is the resistance It is connected to the applied power supply terminal 12 of DC voltage + Vcc via (R ₁ ).

Again, the collectors of the transistors Q ₁₉ and Q ₂ are commonly connected separately through the resistors R ₃ and R ₄ , and the connection point is applied via the resistor R ₅ to the DC voltage-Vee. Is connected to the supplied power supply terminal 13.

Then, the circuits as the resistors R ₁ to R ₅ , the capacitor C ₁ , and the transistors Q ₁ and Q ₂ are used to replace the preamplification circuit 14 of the power amplification circuit. To construct.

In addition, the connection points of the collectors of the transistors Q ₁ and Q ₂ and the resistors R ₃ and R ₄ are respectively provided at bases of the transistors Q ₃ and Q ₄ of the NPN type. Connected. The emitters of the transistors Q ₃ and Q ₄ are commonly connected, and the connection point thereof is connected to the power supply terminal 13 which is electrically connected via the resistor R ₆ . The transistors Q ₃ , Q ₄ , and each collector are connected to the power supply terminal 12 which is electrically connected via the resistors R ₇ and R ₈ , respectively.

The circuits made of the resistors R ₆ to R ₈ , and the transistors Q ₃ and Q ₄ constitute the drive circuit 15 of the power amplification circuit. Again, a connection point of the collector and a resistor (R ₇₎ of the electric one transistor (Q ₃₎ is a collector, an electric power supply terminal (12 a is connected to the base of the NPN-type transistor (Q ₅₎ of the transistor (Q ₅₎ )

In addition, there is connected to the base of the transistor (Q ₅₎ emitter another NPN-type transistor (Q ₆₎ of, the collector of the transistor (Q ₆₎ is connected to an electric power supply terminal (12).

On the other hand, a connection point of the collector and a resistor (R ₈₎ of the electric one transistor (Q ₄₎ is connected to the base of the NPN-type transistor (Q ₇₎ of the transistor emitter transistor of another NPN-type (Q ₇₎ ( Q ₈ ) is connected to the base. The emitter of this transistor Q ₈ is connected to the electrical power supply terminal 13, while the collector of the transistor Q ₈ is connected to the emitter of the transistor Q ₆ , which is connected to the transistor. It is connected to the collector of (Q ₇ ).

The circuits described above as transistors Q ₅ to Q ₈ constitute the output circuit 16 of the power amplifier circuit.

Further, the connection point of the base of the emitter and the transistor (Q ₆₎ of the electrical transistor (Q ₅₎ is via the resistance (R ₃₎ connected to the base of the NPN-type transistor (Q ₉₎ of the. The emitter of the transistor Q ₃ is connected to the base of the transistor Q ₂ constituting the preamplifier circuit 14 which is electrically connected via resistors Q ₁₀ and R ₁₁ in series. In addition, the connection point between the resistors R ₁₀ and R _{11 is} connected between the emitter of the transistor Q ₆ and the collector of the transistor Q ₂ , and an output terminal formed as a jack, for example. It is connected to the inner terminal 171 of 17). The outer terminal 112 of this output terminal 17 is grounded via a resistor R ₁₂ . The connection point between the resistor R ₁₁ and the base of the transistor Q ₂ is grounded through the resistor R ₁₃ .

On the other hand, the connection point between the emitter of the transistor Q ₇ and the base of the transistor Q ₈ is connected to the base of the NPN transistor Q ₁₀ via the resistor R ₁₄ . The emitter of this transistor Q ₁₀ is connected to the power supply terminal 13 which is electrically connected via the resistor R ₁₅ .

In addition, the resistance _{(R 9), (R 10} ), (R 14), (R 14), (R 15) and a transistor _{(Q 9), (Q 10} ) of the circuit is an output circuit (16 Electric as ) to the configuration of each transistor (Q _9), the detection circuit 18 for detecting an extreme operating current (Q _8).

Here, the collector of the transistor Q ₉ described above is connected to the collector of the PNP transistor Q ₁₁ and to the base of the NPN transistor Q ₁₂ . The base of the transistor (Q ₁₁₎ is connected to the base of the transistor (Q _12), to the transistor a power supply terminal 12, electric collector with the emitter and the transistor (Q ₁₂₎ of the (Q ₁₁₎ Connected.

The emitter of the transistor Q ₁₂ described above is connected to the collector of the transistor Q ₁₀ described above, and connected to the base of the transistor Q ₁₃ of the PNP type. It is connected to a meter of the transistor emitter NPN-type transistor (Q ₁₄₎ the emitter of the (Q _13), the base of the transistor (Q ₁₄₎ is connected to a power source terminal 12 with the electric collector.

The collector of the above-described transistor Q ₁₃ is connected to a connection point between the resistors R ₃ , R ₄ and the resistor R ₅ constituting the electric preamplifier circuit 14 described above.

Then, the circuits as the transistors Q ₁₁ to Q ₁₄ described above synthesize the outputs from the transistors Q ₉ and Q 18 of the detection circuit 18 described above to form a relationship described below. The arithmetic feedback circuit 16 which feeds back to the preamplification circuit 14 is comprised.

The overall operation of the power amplifier circuit having the above configuration will be briefly described as follows.

First, it is assumed that the input terminal 11 is supplied with a sinusoidal power amplifier circuit which alternately repeats a positive half cycle and a negative half cycle based on the ground potential, for example. Then, the power amplified signal is supplied to the transistor Q ₁ of the preamplifier circuit 14 via the time constant circuit serving as the capacitor C ₁ and the resistor R ₁ . Here, since the transistors Q ₁ and Q ₂ are common to the emitter, they operate as differential amplifiers, and the negative half cycle and the positive half cycle of the above-described power amplified signal are amplified from the respective collectors, thereby driving the drive circuit 15. ) is output to the transistor _{(Q 3), (Q 4} ). Then, the collectors of the transistors Q ₃ and Q ₄ have a current according to the collector outputs of the transistors Q ₁ and Q ₂ , that is, a negative half cycle and a positive half cycle of the aforementioned amplified signal. The amplification current corresponding to this is output. The collector outputs of the transistors Q ₃ and Q ₄ of the drive circuit 15 are supplied to the transistors Q ₅ and Q ₇ constituting the output circuit 16, respectively. For this reason, in the collector of the transistors Q ₆ and Q ₈ , which are connected to the transistors Q ₅ and Q ₇ and darlington, respectively, the negative half cycle of the above-mentioned power amplified signal is performed. And an amplifying current corresponding to the positive half cycle flows and is output from the output terminal 17. That is, the output circuit 16 has a push-pull configuration for amplifying the positive and negative half cycles of the power amplifier circuit.

Here, the base currents of the transistors Q ₆ and Q ₈ of the output circuit 16, that is, the operating current, _pass through the resistors R ₉ and R _1Δ , respectively. ₉ ) and (Q ₁₀ ), respectively. The collector output currents of the transistors Q ₉ and Q ₁₀ are synthesized as the operational feedback circuit 19, and the synthesized current is output from the collector of the transistor Q _{13 and} supplied to the preamplifier circuit 14 described above. Will be returned.

Here, the transistors Q ₆ and Q ₈ of the output circuit 16 and the transistors Q ₉ and Q ₁₀ of the detection circuit 18 and the transistor Q ₁₃ of the operation feedback circuit 19 described above. Emitters of transistors Q ₁₁ and (Q ₁₃ ) and transistors Q ₁₂ and (Q ₁₄ ), with the current between each collector-emitter of () being (I ₁ ) to (I ₄ ) and (I _F ). Let area ratios be K ₁ and K ₂ , and emitter area ratios of transistors Q ₆ , Q ₈ , transistors Q ₉ , and Q ₁₀ be N.

In doing so, the currents I ₁ to I ₄ and I _{F of the} transistors Q ₆ , Q ₈ , Q ₉ , Q ₁₀ , and Q ₁₃ described above are as follows. It is in the same relationship.

……①

… … ①

,

……②

,

… … ②

The collector current I _F of the transistor Q ₁₃ is returned to the preamplifier circuit 14 so that the above-mentioned (I _F ) is kept substantially constant. Transistor of this reason, the detection circuit (18) (Q _9), (Q ₁₀₎ transistor (Q ₆₎ of the apparent phase output circuit 16 by a, is in the form as (Q ₈₎ control the transistors (Q ₆ ), And the idle currents of (Q ₈ ) also become constant values.

Next, the operations of the resistors R ₉ , R ₁₀ , and R ₁₄ and R ₁₅ which are the features of the present invention will be described in detail. First, the relationship between the currents I ₃ and I _{4 of} the transistors Q ₉ and Q ₁₀ and the output voltage from the output terminal 17 will be shown in FIG. 2 (a). That is, in FIG. 2 (a), the curve A is the current I ₃ of the transistor Q ₉ , and the curve B is the straight line indicated by the dashed-dotted line indicated by the current I ₄ of the transistor Q ₁₀ . C) represents the idle currents of the transistors Q ₆ and Q ₈ .

Here, as described above, the output currents I ₁ and I _{2 of the} transistors Q ₆ and Q ₈ of the output circuit 16 and the transistors Q ₉ and Q of the detection circuit 18, respectively. _The relation between the output currents I ₃ and I ₄ in the ideal state should be as shown in Equation ( ₂ ) in the ideal state. In reality, the parasitic base and emitter resistance of the transistor (Q ₆ ) in the large current region Parasitic resistance is affected. As a result, in the absence of the resistors R ₉ , R ₁₀ , R ₁₄ , and R ₁₅ , the base-emit of each transistor Q ₆ , Q ₈ of the output circuit 16 is absent. The intervoltage is the current value (I ₁ ). The difference occurs more than the proportional relationship in the natural logarithm characteristic of (I ₂ ). However, since the transistors Q ₉ and Q ₁₀ operate in the low current region, their outputs do not include the above difference and cannot accurately detect the operating currents of the transistors Q ₆ and Q ₈ . That is, as a result, there arises a problem that the relation of the above equation (1) is not satisfied, a stable feedback current (I _F ) is not obtained, and a problem that the idle current of transistors (Q ₆ ) and (Q ₈ ) is not stable. there was.

Transistors Q ₉ when there are no resistors R ₉ , R ₁₂ , and R ₁₄ , R ₁₅ , which the curves D and E indicated by dotted lines in FIG. ), And output currents I ₃ ′ and (I ₄ ′) of (Q ₁₀ ).

For this reason, N times the parasitic resistance value of the transistor Q ₆ of the output circuit 16 (where N is the transistors Q ₆ , Q ₉ , and the transistors Q ₉ , Q ₁₀ ). emitter when connected to the transistor _{(Q 9), (Q 10} ) of the area ratio) detection circuit 18, a resistor having a resistance value of the transistor (Q _9), the output of the (Q ₁₀₎ of a transistor (Q _6), (Q ₈ ), the currents I ₃ and I ₄ that accurately detect the operating current are generated. And, the resistance for this is the resistance (R ₉ ), (R ₁₀ ) and (R ₁₄ ), (R ₁₅ ), the resistance (R ₉ ), (R ₁₀ ) and (R ₁₄ ), (R ₁₅₎ In other words, it satisfies the relationship of the above equations ① and ② together with the small current and the large current range, and can maintain stable idling current by obtaining stable feedback current (I _F ).

In addition, the resistance _{(R 9), (R 14} ) has the effect transistor (Q _9), it may even so subtracted by a factor of the current amplification factor β minutes (Q ₁₀₎ when it comes to, as long as he resistor (R ₁₀ ) And (R ₁₅ ) may be increased.

In addition, the output current (I ₁₎ of the power amplifier circuit configured as described above, the output circuit 16, the transistor (Q _6), either the transistor (Q ₆₎ of one of the (Q ₈₎ or (Q ₈₎ of Or if (I ₂ ) becomes 100 times, for example, the output current (I ₂ ) or (I ₁ ) of the other transistor (Q ₈ ) or (Q ₆ ) becomes 1/100 times. Here, the smaller current value (I ₂ ) or (I ₁ ) is as large as possible, which is advantageous in reducing notching distortion or crossover distortion. ) Is good, but good.

For this purpose, the resistance values of the resistors R ₉ , R ₁₀ , R ₁₄ , and R ₁₅ are N times the parasitic resistance of the transistor Q ₆ of the output circuit 16 (where N is a transistor). It may be set _{(Q 6), (Q 8} ) and the transistor (Q _9), so as to have a resistance value over the emitter area ratio of the (Q _10)).

That is, as (1, 2) shows that (I _F ) is constant, the transistor (Q ₉ ) or (on the side detecting the operating current of the transistor (Q ₆ ) or (Q ₈ ) on the side where a large current flows. output current (I ₃₎ of the Q ₁₀₎ or (I ₄₎ is the transistor (Q ₉₎ or the base of (Q ₁₀₎ - resistance of the emitter circuit _{(R 9), (R 10} ) , or (R ₁₄₎ This is because it is smaller than 1 / N by (R ₁₅ ), and the operating current of the transistor Q ₈ or Q ₆ on which the current as small as two minutes flows becomes large.

Here, the relationship between the currents I ₃ and I ₄ of the transistors Q ₉ and Q _{10 at} this time and the output voltage V from the output terminal 17 is shown in FIG. In FIG. 2 (b), the curve F shows the current I ₃ of the transistor Q ₉ , and the curve G shows the current I ₄ of the transistor Q ₁₀ , which is indicated by a dotted line. Output current (I ₃ ) of transistors (Q ₉ ) and (Q ₁₀ ) in the absence of resistors (R ₉ ), (R ₁₀ ), and (R ₁₄ ), (R ₁₅ ), which are energized by (H), (J) ''), (I ₄ ',). That is, as shown in FIG. 2 (b), the larger current among the transistors Q ₉ and Q ₁₀ compared to the absence of the resistors R ₉ , R ₁₀ , and R ₁₄ , R ₁₅ . Transistor Q ₁₀ or Q ₉ on the side through which a small current flows by the amount that the output current I ₃ or I ₄ of the transistor Q ₉ or Q ₁₀ on the side through which the current flows decreases. The output current (I ₄ ) or (I ₃ ) of is increasing.

The output currents I ₁ to I _{4 of the} transistors Q ₆ and Q ₈ of the output circuit 16 and the transistors Q ₉ and Q ₁₀ of the detection circuit 18 are described. ) Is divided into the case of adding the resistors (R ₉ ), (R ₁₀ ), (R ₁₄ ), and (R ₁₅ ), and the case where no addition is made.

However, the table is _{N = 100, R 9, R} 14 = 0 [Ω], R 10, R 15 = 100 [Ω], the transistor as the collector idle current = 10 [mA] of the (Q ₉₎ transistors (Q ₆ ) Shows the case of output current = 1 [A].

Therefore, the current value I ₄ of the transistor Q ₁₀ on the side where the small current flows can be increased by about 13 times as compared with the case where there are no resistors R ₁₄ and R ₁₅ .

And, even if the first degree in the circuit shown in Fig., A collector and an electric displacement of the transistor (Q ₁₃₎ of the operational feedback circuit (19) by interposing the amplifier circuit 14 wareul capacitor unexpected shows a feedback line for connecting a ground do.

In other words, the feedback line may not be bypassed to the ground in an alternating manner.

In addition, according to the embodiment described above, since the output circuit 16 is constituted as the same-polar NPN transistors Q ₆ and Q ₈ , a large current capacity can be obtained, which makes the integrated circuit IC highly suitable.

FIG. 3 shows another embodiment of the present invention, in which half cycles of the precision portion of the power amplified signal on the sine wave are supplied to the input terminals 21 and 22, respectively. In this case, the above-mentioned power amplified signal is supplied to the drive circuit 23 having a differential amplifier circuit configuration by connecting the PNP transistors Q ₂₁ and Q ₂₂ to the common emitter. The amplification current corresponding to the negative half cycle and the positive half cycle of the above-mentioned power amplified signal is output to the collectors of the transistors Q ₂₁ and Q ₂₂ . Here, the collector outputs of the transistors Q ₂₁ and Q ₂₂ of the drive circuit 23 are supplied to the transistors Q ₂₃ and Q ₂₄ of the output circuit 24 having a push-pull configuration. . For this reason, an amplification current for the negative half cycle and the positive half cycle of the aforementioned amplified signal flows through the transistors Q ₂₃ and Q ₂₄ , and is output from the output terminal 25.

Here, the base currents of the transistors Q ₂₃ and Q ₂₄ of the output circuit 24, that is, the operating current, are supplied to the bases of the transistors Q ₂₅ and Q ₂₆ constituting the detection circuit 26, respectively. do. Then, the output current of the transistor (Q _25), (Q ₂₆₎ is synthesized to the base of the transistor (Q ₂₇₎ constituting the operation feedback circuit 27 is supplied, the transistor from the collector of the transistor (Q ₁₇₎ ( Q ₂₈ ) and (Q ₂₉ ) are fed back to the preamplifier circuit 28.

Here, the feedback current I _F and the output currents I ₅ and I ₆ of the transistors Q ₂₅ and Q ₂₆ of the detection circuit 26 satisfy the following equation as described above. I'm making it.

In the circuit shown in FIG. 3, the resistor R ₂₁ connected to the emitter of the transistor Q ₂₆ of the detection circuit 26 is connected to the resistors R ₁₄ and R ₁₅ shown in FIG. 1. It does the same thing. In addition, the resistors corresponding to the resistors R ₉ and R ₁₀ shown in FIG. 1 are not connected to the transistor Q ₂₅ . For this reason, the circuit shown in FIG. 3 has the same effect as the embodiment described above only in terms of the definition of the output voltage V from the output terminal 25. The circuit shown in FIG. It can also be set as a circuit structure.

The feedback line connecting the transistor Q ₂₇ and the preamplifier circuit 28 of the operational feedback circuit 27 may be grounded via a capacitor (not shown). In other words, the above collapsed lines need not be bypassed to the ground interchangeably.

In the circuit shown in FIG. 1 again, instead of the resistors R ₉ , R ₁₀ , R ₁₄ , and R ₁₅ , the base of the transistor Q ₁₀ , the collector, and the transistor Q ₁₃ is used. The same effect as in the above-described embodiment can be obtained by connecting a resistor (not shown) in series with the emitter of the transistor Q ₁₃ and the power supply terminal 12 in series.

로는 되지 않으며, 상기한 삽입저항에 의한 부귀환으로 인하여

보다 작아진다. 따라서, 출력증폭이 크지며, (I₃) 또는 (I₄)의 한쪽이 크게 되더라도, 다른 쪽은 그다지 작아지지 않으며, 트랜지스터(Q₉), (Q₁₀)의 에미터에 저항을 사용한 것과 같은 효과가 얻어진다. 이때의(I₃), (I₄)는 제4도와 같이되며,

의 값은 진폭과 함께 크게된다.In this case, the output current from transistor Q ₁₃ is strictly

Because of the negative feedback caused by the insertion resistance

Becomes smaller. Therefore, if the output amplification becomes large and one side of (I ₃ ) or (I ₄ ) becomes large, the other side is not so small, and the same as using a resistor on the emitters of transistors Q ₉ and Q ₁₀ . Effect is obtained. At this time, (I ₃ ), (I ₄ ) are as shown in FIG.

The value of becomes larger along with the amplitude.

5 shows a modified example of the present invention, in which the output currents of the output transistors Q ₃₁ and Q ₃₂ are detected as diodes D ₁₁ and D ₁₂ , and this detection current is detected by the transistors Q ₃₃ . Transposed as transistors Q ₃₅ and Q ₃₆ , via a Q ₃₄ resistor R ₃₁ , R ₃₂ and an operational feedback circuit 31 as diodes D ₁₃ and D ₁₄ . It feeds back to the amplification circuit 32. Further, the figure _{(Q 37), (Q 38} ) is a cascade Code. It is a buffer transistor.

Therefore, even with such a configuration, the same effects as in the above embodiment can be obtained.

Incidentally, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention.

Therefore, as described in detail above, according to the present invention, it is possible to easily set the idle current, obtain a large output, and also operate stably and reliably, and very good power amplification suitable for integrated circuit (IC). A circuit can be provided.

Claims (1)

First and second transistors for push-pull output, third and fourth transistors for separately detecting operating currents of the first and second transistors, and detection currents of the third and fourth transistors, respectively. Approximately by (I ₃ ), (I ₄ )

In the power amplifier circuit with a feedback circuit which functions an output current (I _F) of the operational circuit and a computing circuit for outputting a current (I _F) so as to maintain approximately constant that is, the electric one of the third and fourth At least one base of the transistor or the electrical calculation circuit. A power amplifier circuit comprising a resistor connected in series to an emitter circuit.

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