KR20250112595A - Resistance variable memory device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a variable resistance memory device and a manufacturing method thereof, and provides a variable resistance memory device including first conductive lines extending in a first direction, second conductive lines extending in a second direction intersecting the first direction, and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, wherein each of the memory cells includes a lower electrode, a switching pattern, a middle electrode, an insulating pattern, a variable resistance pattern, and an upper electrode sequentially stacked between corresponding first and second conductive lines, wherein the insulating pattern is formed to have lower thermal conductivity than the middle electrode and the upper electrode, and the variable resistance pattern is formed in a pillar shape having a ring-shaped horizontal cross-section, wherein a ring-shaped capping insulating pattern surrounding the variable resistance pattern is provided on an outer wall of the variable resistance pattern, and a pillar-shaped buried insulating pattern is provided on an inner wall of the variable resistance pattern.

Description

Resistance variable memory device and method for fabricating the same {Resistance variable memory device and method for fabricating the same}

The present invention relates to a variable resistance memory device and a method for manufacturing the same, and more particularly, to a variable resistance memory device having a cross-point structure and a method for manufacturing the same.

Recently, with the spread of portable digital devices and the increasing need to store digital data, interest in nonvolatile memory devices that do not lose stored data even when power is turned off is increasing.

As semiconductor devices, flash memory devices are widely used because they can be manufactured at low cost based on silicon processes, such as DRAM memory devices. However, flash memory devices have the disadvantages of having relatively low integration, slow operation speed, and requiring relatively high voltage for data storage compared to DRAM memory devices, which are volatile memory devices.

To overcome the shortcomings of such flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) have been proposed. Such next-generation nonvolatile memory devices can operate at relatively low voltages and have fast access times, which significantly offsets the shortcomings of flash memory devices. In particular, magnetic memory devices are attracting attention as next-generation memories because they can have high-speed operation and/or non-volatility characteristics.

As the electronics industry advances, the demand for high integration and/or low power consumption of magnetic memory devices is increasing. Accordingly, many studies are being conducted to meet these demands.

The background technology of this application is disclosed in Patent Publication No. 10-2020-0022567.

The technical problem to be solved by the present invention is to provide a variable resistance memory device with improved electrical characteristics and reliability and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present invention for achieving the above object, a variable resistance memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, wherein each of the memory cells includes a lower electrode, a switching pattern, a middle electrode, an insulating pattern, a variable resistance pattern, and an upper electrode sequentially stacked between corresponding first conductive lines and second conductive lines, wherein the insulating pattern is formed to have lower thermal conductivity than the middle electrode and the upper electrode, and the variable resistance pattern is formed in a pillar shape having a ring-shaped horizontal cross-section, wherein a ring-shaped capping insulating pattern surrounding the variable resistance pattern is provided on an outer wall of the variable resistance pattern, and a pillar-shaped embedded insulating pattern is provided on an inner wall of the variable resistance pattern.

According to one embodiment, the insulating pattern includes a two-dimensional (2D) structured transition metal dichalcogenide (TMDC) material, wherein the transition metal chalcogenide material may include at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, and ReSe2.

In one embodiment, the capping insulating pattern may include a same material as the insulating pattern, and the buried insulating pattern may include silicon oxide.

According to embodiments of the present invention, since a buried insulating pattern is inserted into the inner side of a variable resistance pattern implemented in a pillar shape having a ring-shaped horizontal cross-section, heat transferred from an upper electrode is prevented from spreading overall and is concentrated on the variable resistance pattern, so that heat efficiency can be increased. In particular, when a capping insulating pattern surrounding an outer wall of the variable resistance pattern includes a two-dimensional (2D) structured transition metal dichalcogenide (TMDC) material, heat generated and transferred to the variable resistance pattern is prevented from being horizontally distributed more effectively, so that heat transfer efficiency can be further increased. As a result, current consumption can be reduced, and switching characteristics of the variable resistance pattern can be improved.

In addition, since an insulating pattern having low thermal conductivity is provided between the middle electrode and the variable resistance pattern, the heat generated from the variable resistance pattern can be minimized from affecting other adjacent components.

As a result, it may be possible to provide a variable resistance memory device with improved electrical characteristics and reliability.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.
FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention.
Figures 3a and 3b are cross-sectional views taken along lines I-I' and II-II' of Figure 2, respectively.
Figures 4a and 4b are plan views illustrating the shape of a variable resistance pattern.
FIGS. 5A to 10A are drawings for explaining a method for manufacturing a variable resistance memory element according to one embodiment of the present invention, and are cross-sectional views corresponding to line II' of FIG. 2.
FIGS. 5b to 10b are cross-sectional views corresponding to line II-II' of FIG. 2, illustrating a method for manufacturing a variable resistance memory element according to one embodiment of the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the present embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In this specification, when it is said that an element is “on” another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. Also, in this specification, when it is said that a part “includes” a certain element, this does not mean that the other element is excluded, but rather that the other element can be included, unless otherwise specifically stated.

The terms “about,” “substantially,” and the like, as used throughout this specification, are used in a meaning that is at or near the numerical value when manufacturing and material tolerances inherent in the meanings referred to are presented, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure, which states precise or absolute values to aid understanding of this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.

Referring to FIG. 1, first conductive lines (CL1) extending in a first direction (D1) and second conductive lines (CL2) extending in a second direction (D2) intersecting the first direction (D1) may be provided. The second conductive lines (CL2) may be spaced apart from the first conductive lines (CL1) along a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2). A memory cell stack (MCA) may be provided between the first conductive lines (CL1) and the second conductive lines (CL2). The memory cell stack (MCA) may include memory cells (MC) provided at each of the intersections of the first conductive lines (CL1) and the second conductive lines (CL2). The memory cells (MC) may be arranged two-dimensionally to form rows and columns. Although one memory cell stack (MCA) is illustrated in the present embodiment, embodiments of the present invention are not limited thereto. Memory cell stacks (MCAs) can be provided in multiples and stacked vertically.

Each of the memory cells (MC) may include a switching pattern (SW) and a variable resistance pattern (VR). The switching pattern (SW) and the variable resistance pattern (VR) may be connected in series with each other between a pair of conductive lines (CL1, CL2) connected thereto.

For example, a switching pattern (SW) and a variable resistance pattern (VR) included in each of the memory cells (MC) may be connected in series with each other between a corresponding first conductive line (CL1) and a corresponding second conductive line (CL2). Here, the first conductive line (CL1) may be a word line, and the second conductive line (CL2) may be a bit line, or vice versa. In addition, although FIG. 1 illustrates that the variable resistance pattern (VR) is provided on the switching pattern (SW), embodiments of the present invention are not limited thereto.

Voltage is applied to the variable resistance pattern (VR) of the memory cell (MC) through the first challenge line (CL1) and the second challenge line (CL2), so that current can flow through the variable resistance pattern (VR), and the resistance of the variable resistance pattern (VR) of the selected memory cell (MC) can change depending on the applied voltage.

According to the change in resistance of the variable resistance pattern (VR), the memory cell (MC) can store digital information such as "0" or "1", and the digital information can be erased from the memory cell (MC). For example, data can be written in the memory cell (MC) in a high resistance state "0" and a low resistance state "1". Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell (MC) according to the embodiments of the present invention is not limited to the digital information of the high resistance state "0" and the low resistance state "1" exemplified above, and can store various resistance states.

For example, the variable resistance pattern (VR) may include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistance pattern (VR) is not limited thereto, and may include any variable resistor whose resistance value changes depending on an applied voltage.

As another example, the variable resistance pattern (VR) may include a transition metal oxide layer, in which case at least one electrical passage may be created or destroyed within the variable resistance pattern (VR) by a program operation. When the electrical passage is created, the variable resistance pattern (VR) may have a low resistance value, and when the electrical passage is destroyed, the variable resistance pattern (VR) may have a high resistance value. By utilizing the difference in resistance values of the variable resistance pattern (VR), the variable resistance memory element may store data.

The switching pattern (SW) may be a current control element capable of controlling the flow of current. In the present invention, the switching pattern (SW) may be a selection element having an ovonic threshold switching (OTS) characteristic. That is, the switching pattern (SW) may include a material having an ovonic threshold switching characteristic in which resistance may change depending on the magnitude of a voltage applied to both ends of the switching pattern (SW). Accordingly, when a voltage smaller than the threshold voltage is applied to the switching pattern (SW), the switching pattern (SW) is in a high resistance state, and when a voltage larger than the threshold voltage is applied to the switching pattern (SW), it is in a low resistance state and current starts to flow. In addition, when the current flowing through the switching pattern (SW) becomes smaller than the holding current, the switching pattern (SW) may change to a high resistance state.

Any memory cell (MC) can be addressed by selecting a first challenge line (CL1) and a second challenge line (CL2), and by applying a predetermined signal between the first challenge line (CL1) and the second challenge line (CL2), the memory cell (MC) is programmed, and by measuring a current value through the first challenge line (CL1), information according to the resistance value of a variable resistor constituting the corresponding memory cell (MC) can be read.

Referring to FIGS. 2, 3a, and 3b below, a variable resistance memory device according to one embodiment of the present invention will be described.

FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention. FIGS. 3a and 3b are cross-sectional views taken along lines I-I' and II-II' of FIG. 2, respectively. FIGS. 4a and 4b are plan views for explaining the shape of a variable resistance pattern.

Referring to FIGS. 2, 3A, and 3B, first conductive lines (CL1) and second conductive lines (CL2) may be sequentially provided on a substrate (100). The first conductive lines (CL1) may extend in a first direction (D1) substantially parallel to a top surface of the substrate (100) and may be spaced apart from each other in a second direction (D2) substantially parallel to the top surface of the substrate (100) and intersecting the first direction (D1). The second conductive lines (CL2) may extend in the second direction (D2) and be spaced apart from each other in the first direction (D1). The first conductive lines (CL1) and the second conductive lines (CL2) may be spaced apart from each other in a third direction (D3) perpendicular to the top surface of the substrate (100).

The substrate (100) may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a Si-Ge substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, etc. The substrate (100) may also include a III-V group compound, such as InP, GaP, GaAs, GaSb, etc. Meanwhile, although not shown, a p-type or n-type impurity may be injected into the upper portion of the substrate (100) to form a well.

Each of the first and second challenge lines (CL1, CL2) may include a metal (e.g., copper, tungsten, or aluminum) and/or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

First insulating patterns (102) may be arranged between the first challenge lines (CL1). The first insulating patterns (102) may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

Although not illustrated, an insulating film (not illustrated) may be interposed on the substrate (100). In this case, the first conductive line (CL1) may be formed on the insulating film. In addition, a peripheral circuit (not illustrated) including a transistor, a contact, a wiring, etc. may be formed on the substrate (100). In addition, a lower insulating film (not illustrated) that at least partially covers the peripheral circuit may be formed on the substrate (100).

Memory cells (MC) may be arranged between first conductive lines (CL1) and second conductive lines (CL2), and may be respectively positioned at intersections of the first conductive lines (CL1) and second conductive lines (CL2). The memory cells (MC) may be two-dimensionally arranged along the first direction (D1) and the second direction (D2). The memory cells (MC) may form one memory cell stack (MCA, see FIG. 1).

Each of the memory cells (MC) may include a lower electrode (110), a switching pattern (120), a middle electrode (130), an insulating pattern (140), a variable resistance pattern (180), and an upper electrode (190) that are sequentially stacked, and the stacked structures thereof may be connected in series between a pair of conductive lines (CL1, CL2) connected thereto. In the present embodiment, the first and second conductive lines (CL1, CL2), the switching pattern (120), and the variable resistance pattern (180) may correspond to the first and second conductive lines (CL1, CL2), the switching pattern (SW), and the variable resistance pattern (VR) of FIG. 1.

The lower electrode (110) may be in contact with the first conductive line (CL1), and the upper electrode (190) may be in contact with the second conductive line (CL2). Each of the lower electrode (110) and the upper electrode (190) may be formed of a noble metal such as Ir, Ru, Pd, Au, Pt, a metal oxide such as IrO2, a non-noble metal such as W, Ni, Al, Ti, Ta, TiN, TiW, TaN, or a conductive oxide such as IZO or ITO. The upper electrode (190) may be a heater electrode that applies heat to a variable resistance pattern (180) in contact with its lower surface to change a phase.

Each of the lower electrode (110) and the upper electrode (190) may be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process, but the present invention is not limited thereto. In addition, the lower electrode (110) and the upper electrode (190) may be formed of the same or different materials.

A switching pattern (120) may be provided on the lower electrode (110). The switching pattern (120) is a selection element having ovonic threshold switching (OTS) characteristics and may function as a switch.

In one embodiment, the switching pattern (120) may include a chalcogenide material. The chalcogenide material may include a compound in which at least one of the chalcogen elements Te and Se is combined with at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. For example, the chalcogenide material may include at least one of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe. According to some embodiments, the switching pattern (120) may further include an impurity (for example, at least one of C, N, B, and O).

An intermediate electrode (130) may be provided on the switching pattern (120). The intermediate electrode (130) may electrically connect the switching pattern (120) and the variable resistance pattern (180). The intermediate electrode (130) may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

An insulating pattern (140) may be provided between the middle electrode (130) and the variable resistance pattern (180). The insulating pattern (140) may be formed to have lower thermal conductivity than the middle electrode (130) and the upper electrode (190). For example, the insulating pattern (140) may include a transition metal dichalcogenide (TMDC) material having a two-dimensional (2D) structure. The TMDC material may include at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, and ReSe2.

The TMDC material of the above 2D structure may have a structure in which a plurality of monolayers having a very small thickness, for example, about 0.5 nm or less, are formed, and the plurality of monolayers may be formed to be spaced apart from each other by a predetermined interval, for example, about 0.65 nm, through Van der Waals bonding. Accordingly, since the insulating pattern (140) may have low thermal conductivity, heat generated between the middle electrode (130), the variable resistance pattern (140), and the upper electrode (190) may be prevented from being conducted to adjacent components along the third direction (D3).

The variable resistance pattern (180) may include a material that stores information according to changes in resistance.

According to one embodiment, the variable resistance pattern (180) may include a material capable of a reversible phase change between crystalline and amorphous depending on temperature. For example, the variable resistance pattern (180) may be formed of a compound in which at least one of chalcogenide elements Te and Se is combined with at least one selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. Specifically, the variable resistance pattern (180) may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe.

In another embodiment, the variable resistance pattern (180) may include a material whose electrical resistance changes due to oxygen vacancy or oxygen movement.

In detail, the variable resistance pattern (180) may include at least one of perovskite compounds or conductive metal oxides. For example, the variable resistance pattern (180) may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, or barium-strontium-zirconium oxide. When the variable resistance pattern (180) includes transition metal oxides, the dielectric constant of the variable resistance pattern (180) may be greater than the dielectric constant of the silicon oxide film. As another example, the variable resistance pattern (180) may have a dual structure of a conductive metal oxide and a tunnel insulating film, or a triple structure of a first conductive metal oxide, a tunnel insulating film, and a second conductive metal oxide. The tunnel insulating film may include aluminum oxide, hafnium oxide, or silicon oxide.

According to embodiments of the present invention, the variable resistance pattern (180) may have a ring shape in a planar manner. As an example, the variable resistance pattern (180) may have a horizontal cross-section of a circular ring shape, as illustrated in FIG. 4A. As another example, the variable resistance pattern (180) may have a horizontal cross-section of a square ring shape.

A ring-shaped capping insulating pattern (172) surrounding the variable resistance pattern (180) may be provided on the outer wall of the variable resistance pattern (180) having a horizontal cross-section in the shape of a ring, and a pillar-shaped embedded insulating pattern (174) may be provided on the inner wall.

In one embodiment, the capping insulating pattern (172) and the buried insulating pattern (174) may include the same material. For example, the capping insulating pattern (172) and the buried insulating pattern (174) may both include silicon oxide, or may include the same material as the insulating pattern (140), i.e., a two-dimensional (2D) structured transition metal dichalcogenide (TMDC) material.

In another embodiment, the capping insulating pattern (172) and the buried insulating pattern (174) may include different materials. For example, the capping insulating pattern (172) may include a two-dimensional (2D) structured transition metal dichalcogenide (TMDC) material, and the buried insulating pattern (174) may include silicon oxide.

The upper surfaces of the variable resistance pattern (180, the capping insulation pattern (172) and the buried insulation pattern (174) have the same height and are in contact with the lower surface of the upper electrode (190), and the lower surfaces of the variable resistance pattern (180, the capping insulation pattern (172) and the buried insulation pattern (174) have the same height and can be in contact with the upper surface of the insulating pattern (140).

Since the variable resistance pattern (180) is implemented in a pillar shape having a horizontal cross-section in a ring shape and the embedded insulating pattern (174) is inserted into the inside of the variable resistance pattern (180), the heat transferred from the upper electrode (190) is prevented from spreading overall and is concentrated on the variable resistance pattern (180), so that the heat transfer efficiency can be increased. In particular, when the capping insulating pattern (172) includes a transition metal dichalcogenide (TMDC) material having a two-dimensional (2D) structure, the heat transferred to the variable resistance pattern (180) is prevented from being horizontally dispersed more effectively, so that the heat transfer efficiency can be further increased. As a result, the current consumption can be reduced, and the switching characteristics of the variable resistance pattern can be improved.

Between the memory cells (MC), a second insulating pattern (150), a mold insulating pattern (160), and a third insulating pattern (195) may be laminated and provided. The second insulating pattern (150) may have an upper surface having the same height as an upper surface of the insulating pattern (140), and the mold insulating pattern (160) may have an upper surface having the same height as the upper surfaces of the variable resistance pattern (180), the capping insulating pattern (172), and the buried insulating pattern (174). In addition, the third insulating pattern (195) may have an upper surface having the same height as an upper surface of the upper electrode (190). The first to third interlayer insulating patterns (150, 160, 195) may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

As described, a variable resistance memory device can be provided in which variable resistance memory cells are provided at the cross points of a first challenge line (CL1) and a second challenge line (CL2).

FIGS. 5A to 10A are drawings for explaining a method for manufacturing a variable resistance memory element according to an embodiment of the present invention, and are cross-sectional views corresponding to line I-I' of FIG. 2. FIGS. 5B to 10B are drawings for explaining a method for manufacturing a variable resistance memory element according to an embodiment of the present invention, and are cross-sectional views corresponding to line II-II' of FIG. 2. The same reference numerals may be provided for components substantially the same as those described with reference to FIGS. 2, 3A, and 3B, and redundant descriptions may be omitted.

Referring to FIGS. 5A and 5B, first conductive lines (CL1) extending in a first direction (D1) and spaced apart in a second direction (D2) may be formed on a substrate (100). The first conductive lines (CL1) may be formed by depositing a first conductive film on the substrate (100) and patterning the same. The first conductive film may include a metal or a metal nitride, such as, for example, copper, aluminum, tungsten, titanium, tantalum, titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), or the like. The first conductive film may be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process.

First insulating patterns (102) may be formed between the first challenge lines (CL1). The first insulating patterns (102) may be formed of silicon oxide, silicon nitride, or a combination thereof.

Referring to FIGS. 6A and 6B, a laminated structure including a lower electrode (110), a switching pattern (120), a middle electrode (130), and an insulating pattern (140) may be formed on a substrate (100) on which first conductive lines (CL1) and first insulating patterns (102) are formed. The laminated structure may be formed in an island shape arranged along a first direction (D1) and a second direction (D2).

For example, the lower electrode (110), the switching pattern (120), the middle electrode (130), and the insulating pattern (140) may be formed by sequentially forming a lower electrode film, a switching material film, a middle electrode film, and an insulating material film on a substrate (100) and then patterning them. The patterning may include forming island-shaped mask patterns (not shown) arranged along a first direction (D1) and a second direction (D2) on the insulating material film, and performing an etching process using the island-shaped mask patterns as an etching mask.

Next, a second insulating pattern (150) can be formed between the laminated structures.

Referring to FIGS. 7A and 7B, a mold insulating pattern (160) having a through hole (H) exposing the upper surface of an insulating pattern (140) may be formed on a substrate (150) on which a second insulating pattern (150) is formed. The mold insulating pattern (160) may be formed by forming a mold insulating film on the substrate (150) on which the second insulating pattern (150) is formed, forming a mask pattern exposing an area overlapping with the insulating pattern (140), and then performing an etching process using the mask pattern as an etching mask.

Referring to FIGS. 8A and 8B, a capping insulating pattern (172) surrounding an inner wall of the through hole (H) may be formed within the through hole (H). For example, the capping insulating pattern (172) may be formed by forming a capping insulating film that conformally covers the upper surface of the mold insulating pattern (160) and the inner surface of the through hole (H), and then performing a front anisotropic etching process until the upper surface of the mold insulating pattern (160) and the upper surface of the insulating pattern (140) are exposed.

Referring to FIGS. 9A and 9B, a variable resistance pattern (180) may be formed surrounding the inner wall of the capping insulating pattern (172) within the through hole (H). For example, the variable resistance pattern (180) may be formed by forming a capping insulating film that conformally covers the upper surface of the mold insulating pattern (160), the upper surface of the capping insulating pattern (172), and the inner surface of the through hole (H), and then performing a front anisotropic etching process until the upper surface of the mold insulating pattern (160), the upper surface of the capping insulating pattern (172), and the upper surface of the insulating pattern (140) are exposed.

Referring to FIGS. 10A and 10B, a buried insulating pattern (174) may be formed that fills the remainder of the through hole (H) in which the capping insulating pattern (172) and the variable resistance pattern (180) are formed. For example, the buried insulating pattern (174) may be formed by forming a mold insulating film that fills the remainder of the through hole (H) in which the capping insulating pattern (172) and the variable resistance pattern (180) are formed and covers the upper surface of the mold insulating pattern (160), and then performing a planarization process to expose the upper surface of the mold insulating pattern (160).

Referring again to FIGS. 3A and 3B, upper electrodes (190) may be sequentially formed on variable resistance patterns (180), and a second conductive line (CL2) may be formed that is commonly connected to upper electrodes (190) arranged along the second direction (D2). In addition, a third insulating pattern (195) may be formed on sidewalls of the upper electrodes (190).

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments and application examples described above are exemplary in all respects and are not limiting.

Claims (3)

First challenge lines extending in the first direction;
Second challenge lines extending in a second direction intersecting the first direction; and
Including memory cells provided at each intersection between the first challenge lines and the second challenge lines,
Each of the above memory cells includes a lower electrode, a switching pattern, a middle electrode, an insulating pattern, a variable resistance pattern and an upper electrode, which are sequentially stacked between corresponding first and second conductive lines,
The above insulation pattern is formed to have lower thermal conductivity than the middle electrode and the upper electrode,
The above variable resistance pattern is formed in a pillar shape having a horizontal cross-section in the shape of a ring,
A variable resistance memory element, wherein a ring-shaped capping insulating pattern surrounding the variable resistance pattern is provided on the outer wall of the variable resistance pattern, and a pillar-shaped embedded insulating pattern is provided on the inner wall of the variable resistance pattern. In the first paragraph,
The above insulating pattern comprises a two-dimensional (2D) structure of a transition metal dichalcogenide (TMDC) material,
A variable resistance memory device wherein the transition metal chalcogenide material comprises at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2 and ReSe2. In the second paragraph,
The above capping insulating pattern comprises the same material as the above insulating pattern,
The above-mentioned buried insulating pattern is a variable resistance memory element including silicon oxide.