KR20230042620A - Voltage generating circuit and semiconductor device - Google Patents

Abstract

Provided are a voltage generation circuit and a semiconductor device, which can prevent a leak current without using a DPD mode. The voltage generation circuit of the present invention comprises: a reference voltage generation unit that generates a reference voltage; a leak current monitoring unit that generates a leak current corresponding to the leak current of a peripheral circuit; an output voltage control unit that controls the reference voltage based on the leak current and outputs the controlled reference voltage; a standby voltage generation unit which supplies an internal supply voltage to the peripheral circuit based on the controlled reference voltage; and a voltage drop detection unit which detects that the controlled reference voltage has dropped to a certain level. The output voltage control unit controls the controlled reference voltage according to the detection result of the voltage drop detection unit.

Description

Voltage generating circuit and semiconductor device {VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE}

The present invention relates to a voltage generator circuit and a semiconductor device, and more particularly, to a voltage generator circuit and a semiconductor device in which leakage current is suppressed.

In semiconductor devices, circuit reliability is generally maintained by generating a temperature-compensated voltage corresponding to an operating temperature and operating the circuit. For example, in a memory, if the read current decreases due to a temperature change during data read, the read margin decreases, making it impossible to accurately read data. For this reason, a decrease in read current is prevented by reading data using a temperature-compensated voltage. For example, Japanese Unexamined Patent Publication No. 2021-82094 discloses a circuit scale-reduced voltage generation circuit that does not require an on-chip temperature sensor or a logic for calculating a temperature compensation voltage from the result. are doing

Semiconductor devices such as resistance variable memories can operate with low voltage and constant current, and are suitable for use in mobile devices such as IoT. As the application range to mobile devices and the like widens, the temperature range in the operating environment also expands at the same time. For this reason, a voltage generation circuit generally installed in a semiconductor device can generate a temperature-compensated voltage.

1 is a diagram of an example of a conventional temperature compensated voltage generation circuit. The voltage generator circuit 10 includes a bandgap reference circuit (BGR circuit) 20 that generates a reference voltage Vref that does not depend on fluctuations in the external power supply voltage, and a reference voltage Vref output from the BGR circuit 20. ) and an internal voltage generation circuit 30 that generates an internal supply voltage INTVDD based on .

The internal voltage generating circuit 30 includes an operational amplifier (OP) and a PMOS transistor (Q1). The reference voltage (Vref) is input to the inverting input terminal (-) of the operational amplifier (OP), and the voltage (VN) of the node (N) is input to the non-inverting input terminal (+) by negative feedback. The output of the operational amplifier OP is connected to the gate of the transistor Q1, and the load of the peripheral circuit 40 is connected to the node N. The operational amplifier (OP) controls the gate voltage of the transistor (Q1) so that the voltage (VN) of the node (N) becomes equal to the reference voltage (Vref) (VN = Vref). As a result, the current flowing through the transistor Q1 becomes a constant current that does not depend on the fluctuation of the supply voltage VDD, and the internal supply voltage INTVDD of the constant current is supplied to the peripheral circuit 40 (INTVDD = VN). .

When the operating temperature becomes high while the flash memory is on standby in the standby mode, the leakage current flowing through the peripheral circuit 40 increases. Various integrated circuits using CMOS transistors and the like are formed in the peripheral circuit 40, and the PN junction leakage current of these circuits and the threshold leakage current of the transistor increase with the rise in temperature. Also, since the leak current depends on the voltage, when the internal supply voltage INTVDD increases due to an external factor, the leak current also increases.

In order to suppress leakage current, some semiconductor devices employ a deep power-down mode (DPD mode) to further reduce power consumption than the standby mode. In the DPD mode, the operation of the internal voltage generator circuit 30 is stopped, for example, a switch is provided between the supply voltage VDD and the transistor Q1 to stop the operation of the internal voltage generator circuit 30. Q1 is closed at , cutting off the power supply of the supply voltage (VDD).

However, in the DPD mode, when the supply voltage (VDD) is cut off by the DPD mode, the peripheral circuit 40 floats, and when returning from the DPD mode, the capacitance of the circuit element or wiring of the peripheral circuit 40 is reduced. There is a problem that it needs to be charged, which takes time, and that the next operation cannot be performed quickly.

In order to solve the above problems, the present invention provides a voltage generation circuit capable of suppressing a leak current without using the DPD mode.

A voltage generator circuit according to the present invention includes a reference voltage generator that generates a reference voltage, a leak current monitor that generates a leak current for monitoring corresponding to a leak current in an internal circuit of a semiconductor device, and a leak current for monitoring. and an internal voltage generator that receives the reference voltage controlled by the controller and supplies an internal voltage to the internal circuit based on the controlled reference voltage.

A semiconductor device according to the present invention may include the voltage generator circuit according to any one embodiment of the present invention, and the voltage generator circuit may operate with low power consumption and supply an internal voltage to an internal circuit in a standby mode. there is.

According to the present invention, the reference voltage is controlled based on the leak current for monitoring the leak current of the internal circuit, and the internal voltage is supplied to the internal circuit based on the controlled reference voltage, so that the temperature compensated reference voltage Since it can be generated autonomously, the leakage current of the internal circuit can be minimized.

1 is a schematic diagram of a conventional voltage generation circuit.
2 is a schematic diagram of a voltage generation circuit according to the first embodiment of the present invention.
[Fig. 3] is a block diagram showing the configuration of a voltage generator circuit according to a second embodiment of the present invention.
4A is a schematic diagram of a leak current monitoring unit according to an embodiment of the present invention.
Fig. 4b is a schematic diagram of a leak current monitoring unit according to an embodiment of the present invention.
[Fig. 5] is a schematic diagram of a voltage generation circuit according to a second embodiment of the present invention.
[Fig. 6] is a block diagram of the configuration of a voltage generator circuit according to a third embodiment of the present invention.
Fig. 7 is a schematic diagram of a first example of a voltage generation circuit according to a third embodiment of the present invention.
8 is a schematic diagram of a second example of a voltage generation circuit according to a third embodiment of the present invention.
Fig. 9 is a schematic diagram of a third example of a voltage generation circuit according to a third embodiment of the present invention.
10 is a schematic diagram of a voltage generation circuit according to a fourth embodiment of the present invention.
11 is a schematic diagram of a voltage generation circuit according to a fifth embodiment of the present invention.

The voltage generation circuit according to the present invention is installed in semiconductor memories such as flash memory, dynamic memory, static memory, resistance variable memory, and magnetic memory, or semiconductor devices such as logic and signal processing.

Referring to FIG. 2 , the voltage generator circuit 100 of this embodiment includes a reference voltage generator circuit (BGR circuit) 110 and an internal voltage generator circuit 120 . The voltage generating circuit 100 is, for example, mounted in a flash memory, and supplies the internal supply voltage INTVDD to the peripheral circuit 40 when the flash memory is in a standby state. During this period, the peripheral circuit 40 enters the low power consumption mode, but when a command or the like is input from the outside, it operates in response to the command.

The BGR circuit 110 uses a bandgap voltage, which is a property of silicon of a semiconductor material, to generate a stable reference voltage with low dependence on temperature or power supply voltage fluctuations. The BGR circuit 110 includes first and second current paths between the power supply voltage VDD and GND. The first current path includes a PMOS transistor Q10, a resistor R1, and a PNP bipolar transistor BP1 connected in series, and a second current path includes a PMOS transistor Q20 (transistor Q10) connected in series. ), a resistor R2 (the same resistance value as the resistor R1), a resistor Rf, and a PNP bipolar transistor BP2. The BGR circuit 110 further includes an operational amplifier 112, connects the resistor R1 and the connection node N1 of the bipolar transistor BP1 to the inverting input terminal (-) of the operational amplifier 112, and The connection node N2 of (R2) and the resistor Rf is connected to the non-inverting input terminal (+) of the operational amplifier 112, and the output terminal of the operational amplifier 112 is connected to the gates of the transistors Q10 and Q20. common connection.

The emitter area ratio of the bipolar transistors BP1 and BP2 is 1:n (n is a number greater than 1), and the current density of the bipolar transistor BP1 is n times that of the bipolar transistor BP2. Incidentally, although a bipolar transistor is exemplified here, a diode having an area ratio of 1:n may be used instead of the bipolar transistor.

The operational amplifier 112 controls the gate voltages of the transistors Q10 and Q20 so that the voltage at the node N1 and the node N2 are equal, and accordingly, the same current is applied to the first and second current paths. I _B flows. The voltage V _Rf between the terminals of the resistor Rf is represented by the following formula.

V _Rf = kT/qIn(n)

k is the Boltzmann constant, T is the absolute temperature, and q is the electric charge of the electron.

The current I _B flowing through the resistor Rf is represented by the following equation.

I _B = V _Rf /Rf = T/Rf × k/qln(n)

The temperature-dependent factor is T/Rf, and the current I _B has a positive temperature coefficient.

In addition, when the resistance at the selected tap position of the resistor R2 is the resistor R2', the reference voltage Vref_NTc is expressed by the following equation.

Vref_NTc = V _N2 + I _B R2'

V _N2 is the voltage of node N2.

In a preferred embodiment, the resistor R2 is made of a semiconductor material having a negative temperature coefficient. That is, the resistance decreases as the temperature rises, and the resistance increases conversely as the temperature decreases. The resistor R2 is constituted by, for example, a conductive polysilicon layer doped with high-concentration impurities and an N+ diffusion region. In this embodiment, by appropriately selecting the tap position of the resistor R2, the reference voltage Vref_NTc is given a desired negative temperature coefficient. The tap position or negative temperature coefficient is determined based on how much reference voltage is supplied to the internal voltage generator circuit 120 at the expected maximum temperature.

The internal voltage generator circuit 120 has the same structure as the internal voltage generator circuit 30 shown in FIG. Referring to FIG. 2, the reference voltage Vref_NTc generated by the BGR circuit 110 is input to the inverting input terminal (-) of the operational amplifier (OP) of the internal voltage generating circuit 120, and is input to the non-inverting input terminal The voltage (VN) of the node (N) is input to (+) by negative feedback. The internal voltage generator circuit 120 supplies the internal supply voltage INTVDD generated based on the reference voltage Vref_NTc from the node N to the peripheral circuit 40 .

In this embodiment, the flash memory does not adopt the DPD mode, i.e., does not transition from the standby mode to the DPD mode, and minimizes the leakage current generated in the peripheral circuit 40 during the standby mode. While waiting in the standby mode, when the operating temperature becomes high, the reference voltage Vref_NTc generated in the BGR circuit 110 has a negative temperature coefficient and therefore decreases. When the reference voltage Vref_NTc decreases, the internal supply voltage INTVDD generated by the internal voltage generator circuit 120 also decreases similarly. The leakage current due to the PN junction leak of the peripheral circuit 40 or the off-leak of the transistor increases as the operating temperature rises, but this leak current depends on the internal supply voltage INTVDD and When this decreases, the leakage current also decreases correspondingly.

In this embodiment, since the reference voltage Vref_NTc has a negative temperature coefficient, when the temperature rises, the reference voltage Vref_NTc decreases, and the increased leakage current in the peripheral circuit 40 is offset. Further, since the DPD mode is not employed, the next active operation can be performed without considering the delay time for returning from the DPD mode.

In the first embodiment, the resistor R2 must be trimmed during manufacturing or shipping so that the reference voltage Vref_NTc falls within a certain voltage range when the operating temperature rises. However, in reality, since the increase in leak current is not linear but increases exponentially with a certain temperature as the boundary, the trimming is very complicated. In addition, when the operating temperature exceeds the assumed temperature, the reference voltage Vref_NTc deviates from the above-mentioned constant voltage range. As a result, for example, the reference voltage Vref_NTc of the CMOS transistor of the peripheral circuit 40 If it becomes lower than the minimum operating voltage, the peripheral circuit 40 becomes unable to operate in response to a command or the like input in the standby state. Thus, the second embodiment provides a voltage generator circuit capable of autonomously generating a temperature-compensated reference voltage Vref without trimming the reference voltage generator circuit 110 .

Referring to FIG. 3 , the voltage generator circuit 200 of the second embodiment monitors the reference voltage generator 210 that generates the reference voltage Vref and the leakage current I _{LEAK_PERI} of the peripheral circuit 250 in the standby state. The leak current monitoring unit 220 that generates the corresponding leak current I _LEAK by receiving the reference voltage Vref and the reference voltage controlled based on the leak current I _LEAK generated by the leak current monitoring unit 220 ( It includes an output voltage controller 230 that outputs Vref_C, and a standby voltage generator 240 that generates an internal supply voltage INTVDD based on the controlled reference voltage Vref_C. The peripheral circuit 250 operates with low power consumption by the internal supply voltage INTVDD generated by the standby voltage generator 240 in the standby state, and by the active voltage generator 260 in the active state. It is operated by the generated internal supply voltage (INTVDD).

The reference voltage generator 210 is configured by, for example, the BGR circuit shown in FIG. 2 and provides the reference voltage Vref to the output voltage controller 230 . The leak current monitoring unit 220 generates a leak current I _LEAK having a constant ratio with the leak current I _{LEAK_PERI} generated in the peripheral circuit 250 in the standby state. The peripheral circuit 250 includes various circuits using CMOS transistors and the like, and these circuits, when the flash memory is in a standby mode, operate by the internal supply voltage INTVDD from the standby voltage generator 240 is in On the other hand, along with miniaturization of the transistor, the off-state leakage current (including PN junction leakage and gate leakage) flowing between the source and drain of the transistor increases as the threshold voltage of the transistor decreases. increase, it is necessary to minimize the leakage current of the peripheral circuit 250 in the standby state.

In one aspect, the leakage current monitoring unit 220 includes a CMOS transistor in which at least one PMOS transistor and an NMOS transistor are connected in series in order to monitor the leakage current of the peripheral circuit 250 . The channel width of each of the PMOS transistor and the NMOS transistor has a constant ratio R with respect to the channel width of the sum of the PMOS transistor and NMOS transistor of all the CMOS transistors of the peripheral circuit 250 . In other words, the off-leak current I _LEAK × R of the CMOS transistor of the leak current monitoring unit 220 approximates the off-leak current I _{LEAK_PERI} of the peripheral circuit 250 .

In order to further improve the accuracy of the leak current I _LEAK generated by the leak current monitoring unit 220, the configuration of the CMOS transistor of the peripheral circuit 250 may be considered. That is, in the off-leakage of the CMOS transistor, as shown in (A) of FIG. 4A, the off-leak current I _PMOS when the PMOS transistor is turned off and the NMOS transistor is turned on when the input signal is H level. and, as shown in (B) of FIG. 4A, there is an off-leak current I _NMOS when the PMOS transistor is turned on and the NMOS transistor is turned off when the input signal is at the L level. Since the off-leak current I _PMOS and the off-leak current I _NMOS have different sizes, the total number of CMOS transistors S_P turned off by the PMOS transistors of the peripheral circuit 250 and the total number S_N of CMOS transistors turned off by the NMOS transistors are calculated. The leak circuit A in which the PMOS transistors become off-leak transistors having a constant ratio to the sum of the channel widths of the PMOS transistors of the total number S_P shown in FIG. 4A (C) and the total number S_N shown in FIG. 4A (D) The leak current monitoring unit 220 includes a leak circuit B in which the NMOS transistors become off-leak transistors having a constant ratio to the sum of the channel widths of the NMOS transistors. The leak circuit A and the leak circuit B are connected in parallel, and the sum of the leak current I _PMOS and the leak current I _NMOS becomes the leak current I _LEAK .

The leak current monitoring unit 220 may include a plurality of types of leak circuits in order to generate the leak current I _LEAK considering more leak characteristics of the peripheral circuit 250 . In the peripheral circuit 250, various logic circuits (inverter, AND gate, NAND gate, etc.) using CMOS transistors are formed, and the magnitude of the leakage current is different according to each logic circuit. Therefore, as shown in (A) of FIG. 4B, various leak circuits A, B, C to N having different leak characteristics are prepared, and the leak selected according to the configuration of the peripheral circuit 250 by the trimming signal (Trim). It is okay to make the circuit operate.

For example, leak circuit A generates off-leak current of PMOS transistors, leak circuit B generates off-leak current of NMOS transistors, and leak circuit C generates off-leak currents of PMOS and NMOS transistors. and the leakage circuit N generates an off leakage current of the PMOS transistor of the NAND gate. The trimming signal Trim operates the leak circuits A to N selected by, for example, blowing a fuse.

Further, leak circuits A, B, C, . . . , N each includes a plurality of sets of CMOS transistors in order to scale the ratio of the leakage current of the corresponding logic circuit of the peripheral circuit 250, and a selected number of CMOS transistors among the plurality of sets of CMOS transistors. Transistor works. This selection is performed by the trimming signal Trim. For example, when there is a P group of leakage circuits A connected in parallel, in order to obtain a constant ratio with respect to the leakage current of the corresponding CMOS inverter of the peripheral circuit 250, the number selected from the P group by the trimming signal Trim. The leak circuit A of is operated. For example, the selected number of leakage circuits A are operated by blowing fuses according to the trimming signal Trim.

Leak circuit A, B, C, … , N are connected in parallel and leak currents I _A , I _B , I _C , . . . generated by each leak circuit. , I _N becomes the leakage current I _LEAK . When the operating temperature increases, the leak current I _LEAK increases, and when the operating temperature decreases, the leak current I _LEAK decreases.

In this way, the leak current monitoring unit 220 generates the leak current I LEAK _by monitoring the leak current I _{LEAK_PERI} of the peripheral circuit 250 in the standby state, and transmits the generated leak current I _LEAK to the output voltage control unit ( 230) is provided.

The output voltage controller 230 controls the reference voltage Vref based on the leak current I _LEAK . Specifically, the output voltage controller 230 decreases the reference voltage _{Vref_C} when the leak current I LEAK increases, and increases the reference voltage Vref_C when the leak current I _LEAK decreases. The reference voltage Vref_C controlled by the output voltage controller 230 is provided to the standby voltage generator 240 .

The standby voltage generator 240 has the same structure as the internal voltage generator circuit 120 shown in FIG. 2 , for example. The standby voltage generator 240 receives the reference voltage Vref_C and provides the internal supply voltage INTVDD equal to the reference voltage Vref_C to the peripheral circuit 250 . When the operating temperature of the peripheral circuit 250 rises, the reference voltage Vref_C decreases and the internal supply voltage INTVDD decreases accordingly, so the leakage current I _{LEAK_PERI} of the peripheral circuit 250 is suppressed, and power can save When transitioning from the standby state to the active state, the internal supply voltage INTVDD from the active voltage generator 260 is supplied to the peripheral circuit 250 .

5 is a schematic diagram of a detailed circuit configuration of a voltage generator circuit 200 according to the second embodiment. The reference voltage generator 210 generates a reference voltage Vref using the BGR circuit and provides the reference voltage Vref to the output voltage controller 230 . Incidentally, the reference voltage Vref has a positive temperature coefficient, unlike the reference voltage Vref_NTc of the first embodiment.

Like the standby voltage generator 240, the output voltage controller 230 includes a constant current circuit (a unity gain buffer OP1 and a transistor Q2), and has an external power supply voltage VDD at a node N3. A voltage Vref that does not depend on fluctuations in is generated. A resistor R3 is connected between the node N3 and the node N4, and a constant current I _C is generated at the node N4. The constant current I _C has a constant ratio with respect to the constant current I _{C_PERI} generated by the standby voltage generator 240 (I _{LEAK_PERI} :I _LEAK = I _{C_PERI} :I _C ). That is, the channel width of the transistor Q2 is adjusted at a constant ratio with respect to the channel width of the transistor Q1.

A leak current monitoring unit 220 is connected to the node N4 of the output voltage control unit 230 . Here, an example in which the leak current monitoring unit 220 includes the leak circuit A is shown. The constant current I _C generated at the node N4 flows to GND due to the leak current I _LEAK generated by the leak current monitoring unit 220, and as a result, the constant current I _C and the leak current I _LEAK in the node N4 A reference voltage (Vref_C) controlled by the difference (I _C -I _LEAK ) with and is generated. That is, when the leak current I _LEAK increases due to a temperature rise, the reference voltage Vref_C decreases, and when the leak current I _LEAK decreases due to a decrease in temperature, the reference voltage Vref_C increases, so that the controlled A reference voltage (Vref_C) is autonomously generated.

In the second embodiment, the reference voltage Vref_C is autonomously changed according to the temperature change, but since the leakage current rapidly increases at a certain temperature, the reference voltage Vref_C is the lowest CMOS operation of the peripheral circuit 250. There is a risk of lowering than the voltage. Therefore, in the third embodiment, feedback control is performed so that the reference voltage Vref_C does not fall below the lowest operating voltage of the CMOS.

Referring to FIG. 6 , the voltage generation circuit 200A of the third embodiment includes a voltage drop detection unit 300 and an output voltage control unit 310, and other reference voltage generation units 210 and leak current monitoring Section 220 and standby voltage generation section 240 are the same as in the second embodiment.

The voltage drop detection unit 300 monitors the temperature-compensated reference voltage Vref_C output from the output voltage control unit 310, and determines that the reference voltage Vref_C is a threshold voltage Vth near the lowest operating voltage Vmin of the CMOS. ) is detected (Vref_C-Vmin ≤ threshold voltage (Vth)), and the detection result is provided to the output voltage controller 310.

As in the second embodiment, the output voltage controller 310 outputs the reference voltage Vref_C according to the leak current I _LEAK of the leak current monitoring unit 220, but the reference voltage Vref_C does not correspond to the threshold voltage Vth. When a drop is detected, the reference voltage Vref_C is controlled so that the reference voltage Vref_C becomes greater than the threshold voltage Vth. In one aspect, the output voltage controller 310 cancels the leak current I _LEAK by increasing the constant current I _C flowing from the external power supply voltage VDD to the node N3 to increase the reference voltage Vref_C. In another aspect, the output voltage controller 310 increases the reference voltage Vref_C by offsetting the DC voltage. Accordingly, the operation of the peripheral circuit 250 is guaranteed by preventing the internal supply voltage INTVDD of the standby voltage generating unit 240 from lowering than the lowest operating voltage of the CMOS.

Fig. 7 is a diagram showing a first configuration example of the voltage generator circuit 200A according to the third embodiment of the present invention, and like reference numerals are attached to components identical to those in Fig. 5. As shown in Figs. The voltage drop detection unit 300 monitors the temperature-compensated reference voltage Vref_C of the node N4. The voltage drop detection unit 300 includes a PMOS transistor Q3 having a source connected to a node N4, a resistor R4 passing a constant current connected between the transistor Q3 and the ground, and a resistor between the transistor Q3 and the resistor and inverter IN connected to node N5 between R4. The gate of the transistor Q3 is grounded, and the transistor Q3 is in a conducting state.

When the reference voltage Vref_C is sufficiently higher than the CMOS minimum operating voltage, the transistor Q3 conducts strongly, the node N5 becomes H level, and the output of the inverter IN becomes L level. When the reference voltage Vref_C decreases and Vref_C-Vmin ≤ Vth, the gate-source voltage V _GS of the transistor Q3 decreases, the drain current of the transistor Q3 decreases, and the node N5 becomes the L level, and the output of the inverter (IN) becomes the H level.

The output voltage controller 310 includes an NMOS transistor Q4 connected in parallel with the transistor Q2 between the external supply voltage VDD and the node N3, and the gate of the transistor Q4 has a voltage drop It is connected to the output of the inverter (IN) of the detection unit 300. When the reference voltage Vref_C decreases and the output of the inverter IN becomes H, the transistor Q4 conducts and the current I _ADD is supplied to the node N3. The size of the transistor Q4 is adjusted so that the current I _ADD cancels out the leakage current I _LEAK that rapidly increases with the temperature rise, and the reference voltage Vref_C is higher than the level detected by the voltage drop detection unit 300. do.

When the reference voltage Vref_C sufficiently rises above the lowest operating voltage of the CMOS, the output of the inverter IN of the voltage drop detection unit 300 goes to the L level, and the supply of the current I _ADD is stopped. Incidentally, the supply method of the current I _ADD is not limited to the above, and other methods may be used.

Fig. 8 is a diagram showing a second configuration example of the voltage generator circuit 200A according to the third embodiment of the present invention, and the same reference numerals are attached to components identical to those in Fig. 7 . In the second configuration example, the output voltage controller 310A is a voltage offset unit that increases the voltage of the reference voltage Vref_C in a positive direction according to the output of the inverter IN of the voltage drop detection unit 300 ( 320). The voltage offset unit 320 includes, for example, a pull-up transistor for connecting the reference voltage Vref_C to the external power supply voltage VDD, and the transistor is the H of the inverter IN. It conducts in response to the level output and offsets the reference voltage Vref_C in the positive direction.

When the reference voltage Vref_C is sufficiently higher than the lowest operating voltage of the CMOS, the output of the inverter IN of the voltage drop detection unit 300 becomes L level, and the voltage offset by the voltage offset unit 320 is stopped. Incidentally, the voltage offset method is not limited to the above, and other methods may be used.

Fig. 9 is a diagram showing a third configuration example of the voltage generator circuit 200A according to the third embodiment of the present invention, and the same reference numerals are attached to components identical to those in Figs. 7 and 8. In the third configuration example, the output voltage controller 310B transmits the transistor Q4 for supplying the current I _ADD shown in FIG. 7 and the reference voltage Vref_C shown in FIG. 8 in the positive direction. Each includes a voltage offset unit 320 for offset. Transistor Q4 and voltage offset unit 320, in response to a drop in reference voltage Vref_C being detected by voltage drop detection unit 300, adjust the reference voltage Vref_C so as not to fall below the lowest operating voltage of the CMOS. increases According to the third configuration example, the reference voltage Vref_C can be increased in a short time compared to the first and second configuration examples.

Next, a fourth embodiment of the present invention will be described. Fig. 10 is a schematic diagram of the configuration of a voltage generator circuit according to the fourth embodiment, and the same reference numerals are assigned to components identical to those in Fig. 9. As shown in Figs. In the voltage generator circuit 400 of the present embodiment, the output voltage generator 410 includes the transistors Q10 and Q20 of the BGR circuit of the reference voltage generator 210 and the PMOS transistor Q5 constituting a current mirror. ) is equipped with Transistor Q5 is connected between the external power supply voltage VDD and transistor Q2, and the gate of transistor Q5 is commonly connected to the gates of transistors Q10 and Q20.

Transistor Q5 is configured to a size that has a constant current mirror ratio K with respect to transistors Q10/Q20, and the current I _C flowing through the output voltage control unit 410 is K times iBGR (K is a value greater than or equal to 1) ) becomes In addition, since the current iBGR flowing through the BGR circuit has a positive temperature coefficient, the current I _C flowing through the output voltage controller 410 also has a positive temperature coefficient. For this reason, when the temperature rises, the current I _C increases and, at the same time, the leak current I _LEAK generated by the leak current monitoring unit 220 also increases, and as a result, the reference voltage Vref_C is prevented from rapidly decreasing. Incidentally, the output voltage control unit 410 includes a transistor Q4 that adds a current I _ADD in response to a detection result of the voltage drop detection unit 300 and a voltage offset unit 320, but has a configuration including either one. It is also free

Next, a fifth embodiment of the present invention will be described. Fig. 11 is a schematic diagram of the configuration of a voltage generator circuit according to the fifth embodiment, and the same reference numerals are attached to components identical to those in Fig. 10. As shown in Figs. In the voltage generator circuit 500 of this embodiment, the reference voltage generator 210A has the same structure as that of the first embodiment. That is, the reference voltage generator 210A provides the output voltage controller 410 with the reference voltage Vref_NTc having a negative temperature coefficient.

In this embodiment, when the temperature rises, the reference voltage Vref_NTc decreases, while the current I _C increases and the leakage current I _LEAK also increases. If the increase in current I _C is offset by the leak current I _LEAK , the reference voltage Vref_C decreases due to the decrease in the reference voltage Vref_NTc, and the leak current in the peripheral circuit 250 is suppressed. Incidentally, the output voltage control unit 410 includes a transistor Q4 that adds a current I _ADD in response to a detection result of the voltage drop detection unit 300 and a voltage offset unit 320, but has a configuration including either one. It is also free

The characteristics of the voltage generator circuit of this embodiment are summarized as follows.

1. The internal supply voltage (INTVDD) of the standby voltage generating unit 240 guarantees the minimum operating voltage of the CMOS in the entire range of temperature compensation.

2. At the highest temperature in the temperature compensation range, the internal supply voltage INTVDD of the standby voltage generator 240 is controlled to a minimum DC level.

3. By using a lower internal supply voltage (INTVDD), the junction leak current of the integrated circuit in the peripheral circuit 250, the gate leak current, and the off-leakage current of the transistor can be minimized.

4. Instead of cut-off of the power supply by Deep Power Down Mode (DPD), by maintaining the internal supply voltage (INTVDD) at a lower level, compared to when in Deep Power Down Mode, active operation return time can be shortened.

In addition, in this embodiment, the voltage generation circuit is applied to the standby state of the flash memory, but this is an example, and the present invention can be applied to voltage supply to internal circuits regardless of the standby state. Furthermore, the present invention can be applied to a voltage generation circuit that provides a desired internal voltage to an internal circuit of a semiconductor device other than a flash memory.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

100, 200, 200A, 400, 500: voltage generation circuit
210, 210A: reference voltage generator
220: leak current monitoring unit
230, 310, 310A, 310B, 410: output voltage controller
240: standby voltage generator
250: peripheral circuit
260: active voltage generator

Claims (17)

a reference voltage generator for generating a reference voltage;
a leak current monitor for generating a leak current for monitoring corresponding to a leak current in an internal circuit of the semiconductor device;
a controller for controlling the reference voltage based on the leak current for monitoring;
An internal voltage generator receiving the reference voltage controlled by the control unit and supplying an internal voltage to the internal circuit based on the controlled reference voltage.
A voltage generating circuit comprising a. According to claim 1,
The voltage generating circuit is
A detection unit for detecting that the controlled reference voltage drops to a predetermined level.
Including more,
The control unit,
Based on the detection result of the detection unit, controlling the controlled reference voltage,
voltage generating circuit. According to claim 2,
The certain level,
A voltage higher than the lowest operating voltage of the CMOS transistor of the internal circuit,
voltage generating circuit. According to claim 1 or 2,
The leak current monitoring unit,
Leak-off monitoring transistor for generating the monitoring leak current
including,
The channel width of the monitoring transistor is
It is configured to have a constant ratio with respect to the channel width of the total number of transistors leaking off of the internal circuit,
voltage generating circuit. According to claim 1 or 2,
The leak current monitoring unit,
A plurality of types of off-leak monitoring transistors are included,
The channel width of each monitoring transistor is
It is configured to have a constant ratio with respect to the channel width of the total number of corresponding off-leaking transistors of the internal circuit,
voltage generating circuit. According to claim 4,
The monitoring transistor,
A CMOS transistor in which a PMOS transistor and an NMOS transistor are connected in series,
voltage generating circuit. According to claim 1 or 2,
The leak current monitoring unit,
including a plurality of types of leak circuits and operating a leak circuit selected from among the plurality of types of leak circuits to generate the leak current for monitoring;
voltage generating circuit. According to claim 7,
The leak current monitoring unit,
Selecting the leak circuit based on the trimming signal input from the outside,
voltage generating circuit. According to claim 1 or 2,
The control unit,
Constant current circuit that generates constant current
including,
An output node of the constant current circuit is connected to the leak current monitoring unit;
The controlled reference voltage is output from the output node,
voltage generating circuit. According to claim 9,
When the leak current for monitoring increases, the controlled reference voltage decreases;
When the leak current for monitoring decreases, the controlled reference voltage increases.
voltage generating circuit. According to claim 9,
The constant current circuit,
generating the constant current based on a reference voltage having a negative temperature coefficient;
voltage generating circuit. According to claim 9,
The constant current circuit,
generating the constant current based on a reference voltage having a positive temperature coefficient;
voltage generating circuit. According to claim 2,
The control unit,
Raising the controlled voltage when it is detected by the detection unit that the controlled voltage drops to a certain level,
voltage generating circuit. According to claim 13,
The control unit,
Adding an additional current to the constant current based on the detection result of the detection unit,
voltage generating circuit. According to claim 13,
The control unit,
Based on the detection result of the detection unit, the controlled reference voltage is raised in a positive direction.
voltage generating circuit. The voltage generator circuit according to any one of claims 1 to 3
Including, a semiconductor device. According to claim 16,
semiconductor devices,
Standby mode operating with low power consumption
including,
The voltage generating circuit,
Supplying the internal voltage to the internal circuit when in standby mode,
semiconductor device.

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