KR20170093053A - Volatile memory device and electronic device comprising refresh information generator, providing the information method thereof, and controlling the refresh operation method thereof - Google Patents

Abstract

A volatile memory device according to an embodiment of the present invention may include a memory cell array, a refresh controller, and a refresh information generator. The refresh controller may perform a hidden refresh or a regular refresh on the memory cell array. The refresh information generator may count the number of hidden refreshes and regular refreshes to generate a performance count, and generate refresh information based on the performance count.

Description

TECHNICAL FIELD [0001] The present invention relates to a volatile memory device and an electronic device including a refresh information generator, an information providing method thereof, and a refresh control method thereof. BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] }

The present invention relates to a semiconductor memory device, and more particularly, to a volatile memory device and an electronic device including the refresh information generator, an information providing method thereof, and a refresh control method thereof.

A semiconductor memory device is a device that stores data under the control of a host device such as a computer, a smart phone, a smart pad, or the like. The semiconductor memory device includes a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). As an example of a volatile memory device, a DRAM device performs a refresh operation periodically so as not to lose stored data. Generally, in order to prevent data collision during such a refresh operation, the memory device does not receive a write or read command.

In general, a volatile memory device may be configured in the form of a memory module to provide a host with a high memory capacity. The refresh operation for a plurality of volatile memory devices included in this memory module is managed by the host.

However, control of the refresh operation for each of the memory devices by the host is complicated due to the tendency of the memory module and the memory device to be high in capacity and high in integration. Further, as described above, when the number of refresh commands increases, the efficiency of data processing decreases because the memory device does not receive a write or read command.

It is an object of the present invention to provide a volatile memory device and an electronic device including a refresh information generator for notifying a refresh execution state of a memory device, an information providing method thereof, and a refresh control method thereof.

A volatile memory device according to an embodiment of the present invention may include a memory cell array, a refresh controller, and a refresh information generator. The refresh controller may perform a hidden refresh or a regular refresh on the memory cell array. The refresh information generator may count the number of hidden refreshes and regular refreshes to generate a performance count, and generate refresh information based on the performance count.

According to another embodiment of the present invention, there is provided a method of providing refresh information of a volatile memory device for performing a hidden refresh or a regular refresh, including performing hidden refresh or regular refresh in the volatile memory device, counting the number of hidden refreshes and regular refreshes Generating a count, generating refresh information based on the performance count, and providing the refresh information to the host.

A refresh control method for an electronic device including a volatile memory device that performs a hidden refresh or a regular refresh during a reference time according to another embodiment of the present invention and a host that controls a refresh operation of the volatile memory device is characterized in that in the volatile memory device, Counting the number of regular refresh occurrences to generate a performance count, generating refresh information based on the performance count, providing a performance count or refresh information to the host by a request of the host, And controlling the refresh operation of the volatile memory device with respect to the remaining reference time based on the count or refresh information.

The volatile memory device and the electronic device, the information providing method thereof, and the refresh control method thereof according to the embodiment of the present invention can prevent the unnecessary refresh operation and the occurrence of the refresh command. As a result, the efficiency of the refresh operation control increases, and as a result, the data processing efficiency of the volatile memory device and the memory module increases.

1 is a view showing an electronic device including a memory device according to an embodiment of the present invention.
2 is a block diagram illustrating the memory device of FIG. 1 in accordance with an embodiment of the present invention.
3 is a flowchart illustrating the operation of the memory device of FIG. 2 according to an embodiment of the present invention.
4 is a diagram for explaining the hidden refresh operation.
5 is a block diagram illustrating the memory cell array of FIG. 2, including a plurality of banks, in accordance with an embodiment of the present invention.
FIG. 6 is a block diagram showing the refresh controller shown in FIG. 3 according to an embodiment of the present invention.
FIGS. 7 and 8 are block diagrams illustrating the refresh information generator shown in FIG. 6 according to an embodiment of the present invention.
Fig. 9 is a timing chart for explaining the operation of the refresh information generator of Figs. 7 and 8. Fig.
FIG. 10 is a block diagram illustrating the refresh information generator shown in FIG. 6 according to another embodiment of the present invention.
11 is a timing chart for explaining the operation of the refresh information generator of Fig.
12 is a flow chart illustrating the operation of the electronic device of FIG. 1 according to an embodiment of the present invention.
13 is a timing chart for explaining the operation of the electronic device of Fig. 1 according to the embodiment of the present invention.
14 is a block diagram illustrating a memory device according to another embodiment of the present invention.
15 is a block diagram showing a stacked memory device to which a memory device according to another embodiment of the present invention is applied.
16 and 17 are views showing a memory module according to another embodiment of the present invention.
18 is a block diagram showing a user system to which a semiconductor memory device or a memory module according to an embodiment of the present invention is applied.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a view showing an electronic device including a memory device according to an embodiment of the present invention. Referring to FIG. 1, an electronic device 1 may include a host 10 and a memory device 100. For example, the electronic device 1 may be a single system that includes both the host 10 and the memory device 100. Alternatively, the host 10 and the memory device 100 of the electronic device 1 may be implemented as separate devices.

For example, the host 10 may be a processor circuit or an electronic device, including a general purpose processor or an application processor. Alternatively, the host 10 may be a computing device (e.g., a personal computer, a peripheral device, a digital camera, a PDA (personal digital assistant), a portable media player (PMP) A tablet, a wearable device, or the like). However, these examples are not intended to limit the present invention.

The memory device 100 may store data provided from the host 10 or data to be provided to the host 10. The memory device 100 may be implemented in any storage medium including volatile memory. For example, the memory device 100 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (Z-RAM) And the like. The present invention can be applied to any storage medium including volatile memory. For example, the memory device 100 may include a Unbuffered Dual In-Line Memory Module (UDIMM), a Registered DIMM (RDIMM), a Load Reduced DIMM (LRDIMM), and a Non-Volatile DIMM (NVDIMM). The above assumption is merely an example for facilitating understanding of the present invention, and is not intended to limit the present invention.

Hereinafter, for convenience of explanation, a single DRAM device will be described as an example of the memory device 100 of FIG. However, as described above, it will be readily understood that the present invention can be applied to various storage devices including volatile memory.

The memory device 100 is capable of communicating with the host 10. By way of example, the memory device 100 may be a Universal Serial Bus (USB), a Small Computer System Interface (SCSI), a PCIe, an M-PCIe (Mobile PCIe), an ATA (Advanced Technology Attachment), a PATA Various communication protocols such as ATA (Serial Attached SCSI), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Transmission Control Protocol / Internet Protocol (TCP / IP) (WiMAX), WiMAX, Global System for Mobile communication (GSM), Code Division Multiple Access (CDMA), High Speed Packet Access (HSPA), Bluetooth, Near Field Communication And may communicate with the host 10 based on one or more of the wireless communication protocols. However, these examples are not intended to limit the present invention.

The memory device 100 may receive a command CMD and an address ADDR from the host 10 and perform a write operation, a read operation, or a refresh operation. As described above, the memory device 100 includes a volatile memory. Volatile memory has the characteristic that stored data disappears after a certain time. Thus, in order not to lose the stored data, the volatile memory periodically performs the refresh operation. The refresh operation is an operation of rewriting data stored in the volatile memory according to a predetermined period. The operation of the memory device 100 according to a write operation, a read operation, or a refresh operation is as follows.

In the case of a write operation, the host 10 first provides an active command and a row address to the memory device 100 along with the clock. After a certain time, the host 10 provides write command and column address information to the memory device 100 along with the clock. The host 10 then provides the data to be written to the memory device 100. The memory device 100 writes the provided data in the memory area of the predetermined address.

In the case of a read operation, the host 10 provides the memory device 100 with active command and row address information along with the clock. After a certain time, the host 10 provides the read command and column address with the clock to the memory device 100. Then, after a certain time, the memory device 100 provides the requested data to the memory device 100.

In the case of the refresh operation, the host 10 can provide the refresh command with the clock to the memory device 100 at every regular refresh execution period tREFI. Alternatively, the host 10 may delay the regular refresh execution period tREFI a predetermined number of times, or provide the memory device 100 with a pull-in refresh command. Hereinafter, it is assumed that N normal refreshes are performed for N normal refresh execution periods tREFI by delaying or pulling forward the normal refresh execution period tREFI. In the following description, N normal refresh execution periods tREFI are defined as reference times. In this case, there is no need for the refresh command to be input to the memory device 100 periodically every regular refresh execution period tREFI, and N regular refreshes can be performed at any point where refresh is possible with respect to the N normal refresh execution cycles tREFI . The maximum value of 'N' for memory device 100 is defined by the Joint Electron Device Engineering Council (JEDEC) standard.

The memory device 100 performs a refresh operation on the refresh address generated in the memory memory 100 in accordance with the refresh command. The memory device 100 does not receive a write or read command from the host 10 during the refresh execution time tRFC to perform the refresh operation according to the command. This is because, when the read or write command is performed during the refresh operation, the data of the memory cell accessed by the write or read operation may collide with the data of the memory cells of the row address where the refresh operation is performed. Hereinafter, the normal refresh is defined as a refresh operation performed by the refresh command of the host 10. Further, in addition to the regular refresh, the host 10 can perform the refresh operation for the special purpose by the refresh command by the memory device 100. [ The command for the refresh will be described in Fig.

The memory device 100 performs a refresh operation on all the memory cells of the memory device 100 during one refresh cycle. That is, one refresh cycle includes a plurality of regular refresh periods tREFI and a plurality of reference times. In general, the cycle of the refresh cycle is fixed. The normal refresh execution period tREFI and the refresh execution time tRFC depend on the memory capacity of the memory device 100 since the refresh operation must be performed for all the memory cells of the memory device 100. [ This is defined by the standard literature of the Joint Electron Device Engineering Council (JEDEC). The memory device 100 performs a refresh operation for all the memory cells of the memory device 100 again during a new refresh cycle when one refresh cycle is completed.

The memory device 100 according to the present invention performs a regular refresh by an instruction of the host 10 or a hidden refresh operation that performs a refresh operation when the host 10 does not have an instruction. Hereinafter, the hidden refresh is defined as a refresh operation in which the memory device 100 is executed without a command of the host 10 while executing a write or read command.

The memory device 100 according to the present invention includes a refresh controller 160 for counting the number of times of normal refresh and hidden refresh by controlling a refresh operation so that an access address according to execution of a write or read command does not collide with a refresh address, ). Hereinafter, the count value of the number of times of execution of the normal refresh and the hidden refresh is defined as the execution count. The refresh controller 160 may generate the refresh information (RFR_inf) based on the execution count. Also, the refresh controller 160 may receive the request from the host 10 or provide the refresh information (RFR_inf) to the host 10 at the time of generating the internal flag. Thus, the host 10 can efficiently control the refresh operation for the memory device 100 including a plurality of volatile memories.

2 is a block diagram illustrating the memory device of FIG. 1 in accordance with an embodiment of the present invention. 2, the memory device 100 includes a command decoder 110, an address latch 120, a memory cell array 130, a sense amplifier 131, a column decoder 140, an active controller 150, A controller 160, a row decoder 170, a data input driver 180, a data output driver 190, and a multipurpose register 195.

The command decoder 110 receives various commands via the command pad CMD. The command decoder 110 provides a command to a circuit block such as a column decoder 140, an active controller 150, and a refresh controller 160 or the like.

The address latch 120 receives the address of the memory cell accessed via the address pad ADDR. The address ADDR for selecting the memory cell is stored in the address latch 120, the column decoder 140, the active controller 150, the refresh controller 160 ), And a row decoder 170.

The memory cell array 130 may provide the stored data to the data output driver 190 through the sense amplifier 131. [ Alternatively, the memory cell array 130 may store the data received from the data input driver 180 at a predetermined address through the sense amplifier 131. At this time, the column decoder 140 and the row decoder 170 may provide the address (ADDR) of the memory cell for the data to be input and output to the memory cell array 130.

For example, the memory cell array 130 may include a plurality of banks. Each of the plurality of banks may include a plurality of mat. Each of the plurality of mats may include a plurality of memory cells. In this case, the active controller 150 and the refresh controller 160 may be configured in plural to control each of the plurality of banks. This configuration will be described with reference to FIG.

The active controller 150 generates an active address and an active signal according to the write or read operation by the address ADDR and the command CMD provided from the address latch 120 and the command decoder 110 and outputs the active address and the active signal to the row decoder 170 to provide.

Similar to the active controller 150, the refresh controller 160 of the present invention generates an active address and an active signal, and compares the hidden refresh address and the active address. The refresh controller 160 generates a refresh active signal based on the comparison value and provides it to the row decoder 170. The refresh controller 160 generates a row address for performing a normal refresh or a hidden refresh and provides the row address to the row decoder 170. In addition, the refresh controller 160 of the present invention counts the number of times of performing the normal refresh and the hidden refresh to generate the execution count, and generates the refresh information (RFR_inf) based on the execution count. The refresh controller 160 may provide the generated refresh information RFR_inf to the multipurpose register 195. [ For example, the refresh information RFR_inf may include a run count, a hidden refresh execution count, or a refresh break flag. The hidden refresh execution count, the execution count, and the refresh interrupt flag will be described with reference to FIGS. 7, 8, and 10, respectively.

The row decoder 170 controls the operation of the memory cell array 130 through the provided active address, an active signal, a refresh active signal, and a refresh address. The data input driver 180 may receive the data provided through the data pad DQ and provide the data to the sense amplifier 131. [ The data output driver 190 may output the data stored in the memory cell array 130 through the data pad DQ. Although not shown, the data input driver 180 can receive the data strobe signal through the data strobe pad (DQS) upon receiving the data. Further, the data output driver 190 can output the data strobe signal through the data strobe pad DQS at the time of outputting the data.

The multipurpose register 195 may store internal processing information according to the purpose. Accordingly, the multipurpose register 195 can receive and store the refresh information (RFR_inf) from the refresh controller 160. Also, in the MPR (Multi-Purpose Register) read mode mode defined in the JEDEC standard document, the refresh information (RFR_inf) stored in the multipurpose register 195 is provided to the host 10 via the data output driver 190 .

The reset signal may be provided by a command received from the host 10 via the command pad CMD and the command decoder 110. [ Thus, the refresh information (RFR_inf) and the stored value of the multipurpose register 195 can be initialized aperiodically at the request of the host 10. Alternatively, the above-described reset command may be periodically received from the host 10. That is, the refresh information (RFR_inf) and the stored value of the multipurpose register 195 can be periodically initialized at every reference time by the reset command received from the host 10. [

When the memory device 100 is a DRAM device, the memory device 100 operates in synchronization with the clock. Therefore, a configuration such as a clock buffer, a delay fixing circuit, a duty correction circuit, and the like can be added. However, since this is not related to the present invention, a description thereof will be omitted.

3 is a flowchart illustrating the operation of the memory device of FIG. 2 according to an embodiment of the present invention. Fig. 3 will be described with reference to Figs. 1 and 2. Fig. Referring to Fig. 3, the memory device 100 may generate refresh information (RFR_inf) and provide the generated refresh information (RFR_inf) to the host 10.

In step S110, the memory device 100 performs a refresh operation. As described above, the memory device 100 can perform the normal refresh operation in response to the refresh command of the host 10. [ Alternatively, the memory device 100 may perform a hidden refresh operation in addition to the regular refresh.

In step S120, the memory device 100 counts the number of hidden refreshes and regular refreshes to generate a performance count, and generates refresh information (RFR_inf) based on the performance count. The generated refresh information (RFR_inf) may be stored in the multipurpose register 195. As described above, the refresh information RFR_inf may include a performance count, a hidden refresh execution count, or a refresh end flag.

In step S130, the memory device 100 determines whether or not it has received a request for providing refresh information from the host 10. [ If the request is not received (No direction), the memory device 100 performs step S130 again. However, even in this case, the memory device 100 can additionally perform the hidden refresh or the regular refresh and update the refresh information (RFR_inf). The updated refresh information (RFR_inf) is stored again in the multipurpose register 195. If the request is received (Yes direction), the memory device 100 performs step S140.

In step S140, the memory device 100 provides the host 10 with refresh information (RFR_inf). The memory device 100 provides the host 10 with the refresh information RFR_inf stored in the multipurpose register 195 in accordance with the request of the host 10 and the address of the multipurpose register 195. [ However, depending on the nature of the refresh information RFR_inf, the memory device 100 may be configured to skip step S130 and perform step S140. For example, the refresh end flag contained in the refresh information (RFR_inf) can be provided to the host 10 without request after generation. This is to provide the host 10 with a refresh end flag to the host 10 even when there is no request from the host 10 to prevent the execution of an additional refresh operation within the remaining reference time. Thus, power consumption of the memory device 100 can be prevented, and unnecessary command generation can be prevented. However, this is an example, and the refresh end flag can also be set to be provided to the host 10 only at the request of the host 10.

As described above, the memory device 100 may reset the refresh information (RFR_inf) and the multipurpose register 195. This is because the refresh information (RFR_inf) stored in the multipurpose register 195 is valid only for the reference time.

4 is a diagram for explaining the hidden refresh operation. Fig. 4 will be described with reference to Fig. As described above, the memory cell array 130 may include a plurality of banks. Here, the first bank (Bank0) is illustrated by way of example. The first bank Bank0 may include first through n + 1 matrices MAT0 through MATn and first through n + 1 sense amplifier arrays SA0 through SAn. The first to (n + 1) th sense amplifier arrays SA0 to SAn may constitute a sense amplifier 131. [ The hidden refresh operation in the first bank (Bank0) can be applied to each of the plurality of banks constituting the memory cell array (130).

The first to (n + 1) -th mat (MAT0 to MATn) may each include a plurality of word lines. The selection of the word line is determined by the row address. Each of the plurality of word lines includes a plurality of memory cells. The stored data of a plurality of memory cells connected to one word line is sensed by an adjacent sense amplifier.

The general data sensing operation is as follows. For example, the data of the cell connected to the first bit line (BL0) of the memory cells connected to the first word line (WL1_0) of the second mat (MAT1) is connected to the first sense amplifier of the first sense amplifier array Not shown). In order to compare the data of the selected cell with the reference voltage, a first sense amplifier (not shown) of the first sense amplifier array SA0 is connected to the first pre- And receives the voltage of the bit line BL0. The data of the cell connected to the second bit line BL1 of the first word line WL1_0 of the second mat MAT1 is sensed by a first sense amplifier (not shown) of the second sense amplifier array SA1 . The sense amplifier selected for sensing data is determined by the structure of the memory cell array.

Hereinafter, the hidden refresh operation will be described. First, the memory device 100 is connected to the first bit line BL0 of the first word line WL1_0 of the second mat MAT1 (hereinafter referred to as the first memory cell of the second mat MAT1) ) Is accessed to perform a read operation. In general, a memory device 100 driven by a DDR (Double Data Rate) method reads and writes a plurality of data at the same time by prepatching data in order to improve the reading or writing speed. That is, when the memory device 100 is a memory device operating in the DDR3 scheme, the memory device 100 performs a prefetch operation on 8 bits (2 ^ 3). The memory device 100 includes a first memory cell and a second memory cell coupled to the second to eighth bit lines BL1 to BL7 of the first word line WL1_0 of the second mat MAT1, (Hereinafter, referred to as second to eighth memory cells of the second mat MAT1, respectively) to perform a read operation. In this case, each data is sensed by the adjacent first and second sense amplifier arrays SA0 and SA1.

It is assumed that the memory device 100 performs a refresh operation on each of the first word lines WL0_0 and WL2_0 for the first or third mat MAT0 and MAT2 together with the above-described read operation. Generally, a refresh operation is performed on all memory cells connected to the selected word line. That is, all the memory cells connected to the first word line WL0_0 of the first mat MAT0 (hereinafter referred to as the first to the (n + 1) th memory cells of the first mat MAT0) (Hereinafter referred to as the first to the (n + 1) th memory cells of the third mat MAT2, respectively) connected to the first word line WL2_0 of the first mat MAT2.

To perform the refresh operation, data of the first memory cell of the first mat (MAT0) is sensed by a first sense amplifier (not shown) of the first sense amplifier array SA0. In order to perform a read operation, data of the first memory cell of the second mat (MAT1) is also sensed by a first sense amplifier (not shown) of the first sense amplifier array SA0. As described above, the sense amplifier must receive the data of the memory cell and the reference voltage to perform the sensing operation. In this case, since the corresponding sense amplifier receives two pieces of data, it is not possible to perform data comparison with respect to the reference voltage.

This problem also occurs in the second sense amplifier (not shown) of the second sense amplifier array SA1. That is, the second sense amplifier (not shown) of the second sense amplifier array SA1 receives the data of the second memory cell of the second mat MAT1 and the data of the second memory cell of the third mat MAT2 as inputs . Therefore, the corresponding sense amplifier can not perform data comparison with respect to the reference voltage. This occurs in the same manner for the third to eighth memory cells of the second mat MAT1.

Thus, the hidden refresh operation is performed on a mat of non-contiguous mats with addresses accessed according to a write operation or a read operation. For example, in the above-described example, a hidden refresh may be performed on the fourth mat to the (n + 1) -th mat (MAT3 to MATn). In this case, the data line used at the time of inputting / outputting the accessed data according to the write or read operation must be controlled so that the mat performing the hidden refresh operation is not connected. The operation and configuration of the refresh controller for generating the address of the hidden refresh will be described with reference to FIG.

5 is a block diagram illustrating the memory cell array of FIG. 2, including a plurality of banks, in accordance with an embodiment of the present invention. Referring to FIG. 5, the column decoder 140, the active controller 150, the refresh controller 160, and the row decoder 170 of FIG. 1 each include a memory cell array 130 and a sense amplifier (131).

That is, the memory cell array 130 includes first to n-th memory cell arrays 130_1 to 130_n, the sense amplifier 131 includes first to n-th sense amplifiers 131_1 to 131_n, The refresh controller 140 includes first to nth column decoders 140 and the active controller 150 includes first to nth active controllers 150_1 to 150_n, n refresh controllers 160_1 to 160_n, and the row decoder 170 may include first to nth row decoders 170_1 to 170_n.

Each of the first to nth refresh controllers 160_1 to 160_n may perform a hidden refresh operation on each of the first to nth banks (Bank1 to Bankn). 4, when the active address conflicts with the refresh address for one bank, the first through the n-th refresh controllers 160_1 through 160_n are turned on for all of the first through nth banks Bank1 through Bankn It can be configured not to perform the hidden refresh. Alternatively, the first through the n-th refresh controllers 160_1 through 160_n may be configured to perform a hidden refresh on the remaining banks in which addresses other than the corresponding banks do not collide. Operations of the above-described configurations for the first through n-th banks (Bank1 through Bankn) except for the description described with reference to FIG. 5 are the same as those described with reference to FIG. 1 through FIG. 5, and a description thereof will be omitted.

FIG. 6 is a block diagram showing the refresh controller shown in FIG. 3 according to an embodiment of the present invention. 6, the refresh controller 160 may include a refresh address generator 161, an address comparator 162, logic sum (OR) logic, and a refresh information generator 163. As described above with reference to FIG. 4, the refresh controller 160 generates a signal for performing a hidden refresh operation by determining whether the active address conflicts with the refresh address, counts the number of hidden refreshes and normal refreshes, Information.

The refresh address generator 161 generates a row address for performing the refresh operation. In general, the refresh operation is performed sequentially with respect to the row address. For example, in this case, the refresh address generator 161 may include a counter. The refresh address generator 161 generates a refresh address ADD_rfr and provides the refresh address ADD_rfr to the address comparator 162 (step (1)).

The address comparator 162 is supplied with an active signal ACT and an active address ADD_act according to a write command or a read command. The address comparator 162 determines whether the provided active address ADD_act and the refresh address ADD_rfr conflict with each other and generates a hidden refresh active signal RFR_H (step 2).

The logic sum logic OR receives the hidden refresh active signal RFR_H and the normal refresh active signal RFR to perform a logical OR operation and generates a refresh active signal RFR_en.

Next, the address comparator 162 receives the refresh active signal RFR_en and provides the refresh address ADD_rfr generated in operation 1) to the row decoder 170 (operation 4). Further, the address comparator 162 receives the refresh active signal RFR_en and updates the refresh address ADD_rfr. The row decoder 170 of FIG. 2 receives and decodes the refresh address ADD_rfr and performs a refresh operation on the corresponding refresh address ADD_rfr of the memory cell array 130 according to the refresh active signal RFR_en.

The refresh information generator 163 receives the refresh active signal RFR_en and generates the refresh information RFR_inf. Accordingly, the refresh information generator 163 may also be initialized by the reset signal RST provided from the host 10 periodically or periodically at every reference time. Hereinafter, a description thereof will be omitted. An exemplary configuration of the refresh information generator 163 will be described with reference to Figs. 7, 8, and 10. Fig.

FIG. 7 and FIG. 8 are block diagrams showing the refresh information generator shown in FIG. 6 according to the embodiment of the present invention. 7 and 8 will be described with reference to Fig.

Referring to Fig. 7, the refresh information generator 163a may include an oscillator 164 and a refresh counter 165. Fig. The refresh information generator 163a of FIG. 7 may generate a performance count or a hidden refresh performance count.

The oscillator 164 provides a count-up signal to the refresh counter 165 every regular refresh execution period tREFI. For example, the regular refresh execution period tREFI may be provided from the host 10.

The refresh counter 165 is provided with a count-up signal and a refresh active signal RFR_en. The refresh counter 165 raises the count value in accordance with the count rise signal and decreases the count value in accordance with the refresh active signal RFR_en. The refresh counter 165 outputs the generated count value as the refresh information RFR_inf. The change of the refresh information (RFR_inf) with time will be described with reference to Fig. The count value means the number of times the hidden refresh operation has been performed. Hereinafter, this count value is defined as the hidden refresh execution count. Based on the corresponding refresh information RFR_inf, the host 10 can calculate the number of refreshes to be performed within the remaining reference time.

In addition, the refresh counter 165 may count the refresh active signal RFR_en to generate a performance count. That is, the refresh information RFR_inf may include a hidden refresh count and a performance count.

Referring to Fig. 8, the refresh information generator 163b may include a refresh counter 165. Fig. As described in FIG. 7, the refresh counter 165 of FIG. 8 may count the refresh active signal RFR_en to generate a performance count. In this case, the refresh information RFR_inf may include a performance count.

The refresh information (RFR_inf) generated by the refresh information generators 163a and 163b in Figs. 7 and 8 can be stored in the multipurpose register 195. [ Then, at the request of the host 10, the refresh information (RFR_inf) stored in the multipurpose register 195 can be provided to the host 10. [ The refresh counter 165 of FIGS. 7 and 8 may be initialized by a reset signal RST.

Fig. 9 is a timing chart for explaining the operation of the refresh information generator of Figs. 7 and 8. Fig. Fig. 9 will be described with reference to Figs. 2, 7 and 8. Fig. Referring to Fig. 9, the refresh information generators 163a and 163b of Figs. 7 and 8 can update the refresh information (RFR_inf) each time the execution of the hidden refresh or normal refresh is completed. Then, whenever the refresh information (RFR_inf) is updated, the refresh information (RFR_inf) can be provided and stored in the multipurpose register 195. Hereinafter, a description thereof will be omitted. As described above with reference to FIG. 1, in the following, N normal refresh execution periods tREFI are defined as reference times. The reference time is constituted by a time interval from t0 to t7. After this, the new reference time starts from t7.

In the example of Fig. 9, the memory device 100 receives the refresh command REF from the host 10 every regular refresh execution period tREFI. Each of the plurality of normal refresh execution periods tREFI includes a refresh execution time tRFC. The refresh execution time tRFC is the minimum time for the memory device 100 to perform the normal refresh. During the refresh execution time tRFC, the memory device 100 does not receive a command related to an active operation such as writing or reading. Accordingly, during the refresh execution time tRFC, the memory device 100 receives the deselect signal DES and performs only the refresh operation. The operations of the refresh information generators 163a and 163b shown in FIGS. 7 and 8 are as follows.

At time t0, the memory device 100 receives the refresh command REF. Then, the memory device 100 performs a normal refresh. For the refresh information generator 163a of Fig. 7, the refresh counter 165 receives the refresh active signal RFR_en accordingly and generates a fall count. In addition, the refresh counter 165 receives the rising count from the oscillator 164 as the normal refresh execution period tREFI is started. Thus, the refresh counter 165 outputs a count of '0' as the refresh information RFR_inf. In this case, since the normal refresh operation is being performed, the hidden refresh operation is not performed.

For the refresh information generator 163b in Fig. 8, the refresh counter 165 receives the refresh active signal RFR_en accordingly and outputs a count of '1' as the refresh information RFR_inf.

At time t1, the memory device 100 receives a valid command (Valid) such as a write or read command. Although not shown, memory device 100 receives address information for valid commands. The memory device 100 performs an active operation according to the valid command on the received address. At this time, it is assumed that the received address does not conflict with the refresh address. Hence, the hidden refresh active signal RFR_H is generated. Thus, for the refresh information generator 163a in Fig. 7, the refresh counter 165 receives the refresh active signal RFR_en and generates a fall count. Accordingly, the refresh counter 165 outputs a count of '-1' as the refresh information RFR_inf.

With respect to the refresh information generator 163b of Fig. 8, the refresh counter 165 receives the refresh active signal RFR_en accordingly and outputs a count of '2' as the refresh information RFR_inf.

At time t2, the memory device 100 receives a valid command (Valid) including a write or read command at the same time as the time t1. However, in this case, the received refresh operation signal RFR_H may not be generated due to a collision between the received address and the refresh address. Thus, for the refresh information generator 163a in Fig. 7, the refresh counter 165 does not update the count and maintains the previous count '-1'. The refresh information generator 163a repeats the operation of the plurality of normal refresh execution periods tREFI until time t3. For the refresh information generator 163b in Fig. 8, the refresh counter 165 does not update the count, but retains the previous count '2'.

At the time t3, according to the previous normal refresh or hidden refresh operation, the refresh counter 165 of the refresh information generator 163a of FIG. 7 outputs the count of '-i' as the refresh information RFR_inf. The refresh counter 165 of the refresh information generator 163b of FIG. 8 counts the number of 'N-1' times of normal refresh and the number of times of the hidden refresh of 'i' performed before time t3, and outputs the count of i 'as refresh information RFR_inf.

At time t4, the memory device 100 may perform a hidden refresh. Accordingly, for the refresh information generator 163a in Fig. 7, the refresh counter 165 outputs the count of '- (i + 1)' as the refresh information RFR_inf. The refresh counter 165 of the refresh information generator 163b of Fig. 8 outputs the count of (N-1) + i + 1 'as the refresh information RFR_inf.

At the time t5, the refresh counter 165 of FIGS. 7 and 8 performs the same operation as the time t3. Accordingly, the refresh counter 165 of '7' outputs '- (i + 1)' and the refresh counter 165 of FIG. 8 outputs '(N) + i + 1'. At the time t6, the refresh counter 165 of FIGS. 7 and 8 performs the same operation as the time t4. As a result, the refresh counter 165 of '7' outputs '- (i + 2)' and the refresh counter 165 of FIG. 8 outputs '(N) + i + 2'. The host 10 can be provided with the refresh information RFR_inf according to each time point by the refresh information request. Accordingly, the host 10 can receive information on the total number of times of refresh execution or the number of times of performing the hidden refresh according to each time point, and can control a refresh command for the memory device 100 based on the information. A method of controlling the refresh command of the host 10 will be described with reference to Figs. 12 and 13. Fig.

At time t7, the memory device 100 starts a refresh operation for a new reference time. For example, as described above, the memory device 100 can receive the reset command with the refresh command refresh command REF at a period of the reference time. The refresh information (RFR_inf) and the stored value of the multipurpose register 195 may be periodically initialized by a reset signal. This reset operation must be performed before the refresh information (RFR_inf) generation operation of the refresh information generators 163a and 163b in FIGS. 7 and 8. This is because, in response to the first refresh command REF for the new reference time, the refresh information generators 163a and 163b must newly generate the initialized refresh information RFR_inf. As described above, the reset signal can be provided by the command pad CMD and the command received via the command decoder 110. [ However, this is an example, and as described above, the reset signal can be provided by the command of the host 10 even before the time t7 when the new reference time starts.

FIG. 10 is a block diagram illustrating the refresh information generator shown in FIG. 6 according to another embodiment of the present invention. Fig. 10 will be described with reference to Fig. Referring to FIG. 10, the refresh information generator 163c of FIG. 10 may include a flag generator 166. FIG.

The flag generator 166 is provided with a refresh request count RFR_dnd and a refresh active signal RFR_en. The refresh request count RFR_dnd indicates the number of refreshes to be performed for each of the plurality of banks of the memory cell array 130 of FIG. 1 during one reference time. For example, the refresh request count RFR_dnd may be defined as a value obtained by dividing the reference time by the regular refresh execution period tREFI. For example, the refresh request count RFR_dnd may have a value of N for a reference time which is N regular refresh execution periods (tREFI).

For example, the refresh request count RFR_dnd may be provided from the host 10. Alternatively, the refresh information generator 163c may further include a counter (not shown) for generating a refresh request count RFR_dnd. In this case, the counter (not shown) may generate the refresh request count RFR_dnd by receiving the reference time and the normal refresh execution period tREFI from the host 10.

The flag generator 166 counts the refresh active signal RFR_en and generates a performance count. The flag generator 166 may output the execution count as the refresh information RFR_inf. The flag generator 166 then generates a refresh end flag if the performance count is greater than or equal to the refresh request count (RFR_dnd). The flag generator 166 may output the refresh end flag as the refresh information RFR_inf. That is, the refresh end flag means that all N refresh operations have been performed within the reference time. The flag generator 166 may output the execution count included in the refresh information RFR_inf. In this case, the refresh information RFR_inf may include a run count and a refresh end flag.

3, the refresh end flag may be provided to the host 10 within a certain period of time after generation even if there is a request from the host 10 or there is no request from the host 10. For example, the refresh information generator 163 may be configured to include one or a combination of one or more of the refresh information generators 163a, 163b, and 163c of FIGS. 7, 8, and 10. FIG.

11 is a timing chart for explaining the operation of the refresh information generator of Fig. Fig. 11 will be described with reference to Figs. 2 and 10. Fig. Referring to Fig. 11, the refresh information generator 163c of Fig. 10 generates a refresh end flag and outputs it as refresh information (RFR_inf) when the number of times of execution of the hidden refresh or normal refresh is equal to or larger than the refresh request count (RFR_dnd) . The definitions of the reference time, the refresh command REF, the valid command, the normal refresh execution period tREFI and the refresh execution time tRFC defined by the N normal refresh execution periods tREFI are the same as those described with reference to FIG. 9 same. Therefore, a description thereof will be omitted.

In FIG. 11, it is assumed that the refresh request count RFR_dnd is 'N'. The refresh information generator 163c may generate a performance count, in which case the refresh information (RFR_inf) may include a performance count or a refresh end flag. At this time, whenever the execution count is updated, the refresh information (RFR_inf) including the execution count can be provided to the multipurpose register 195 and stored. Alternatively, the refresh end flag may not be stored in the multipurpose register 195, but may be provided directly to the host.

At time t0, the memory device 100 performs a normal refresh operation in accordance with the refresh command REF, and the flag generator 166 is supplied with the refresh active signal RFR_en accordingly. The flag generator 166 updates the execution count to '1'. In this case, the refresh end flag is not generated. The flag generator 166 outputs the execution count as the refresh information RFR_inf.

At time t1, the memory device 100 performs a hidden refresh operation, and the flag generator 166 updates the value of the execution count to '2'. At time t2, the memory device 100 does not perform the hidden refresh operation, and the flag generator 166 maintains the value of the execution count '2'. At t2 to t3, the memory device 100 can perform a plurality of regular refresh or hidden refresh operations. At the time t3, according to the previous normal refresh or hidden refresh operation, the flag generator 166 outputs the count value of 'N-1' as the refresh information (RFR_inf).

At time t4, the memory device 100 can perform the hidden refresh operation, and thus the refresh information (RFR_inf) becomes 'N'. Thus, the flag generator 166 generates a refresh end flag. As described above, the refresh end flag can be provided to the host 10 within a certain period of time after the generation even if there is a request from the host 10 or there is no request from the host 10. Thus, in response to the refresh end flag, the refresh operation of the memory device 100 can be controlled such that the host 10 stops providing the refresh command REF or does not perform the hidden refresh. A detailed description thereof will be described with reference to FIG.

At time t5, a new normal refresh execution period tREFI is started. However, since there is no provision of the refresh command REF after the refresh end flag is provided to the host 10, the memory device 100 can receive a valid command (Valid). This is the same at t6 and t7. Therefore, the memory device 100 can perform an operation according to a valid command (Valid) instead of performing the refresh operation, thereby increasing the data processing efficiency of the memory device 100. [

At time t8, the memory device 100 can be provided with a reset signal and a refresh command REF for a new reference time, as at time t7 in FIG. The subsequent operation is the same as described in t1 to t7.

12 is a flow chart illustrating the operation of the electronic device of FIG. 1 according to an embodiment of the present invention. 12, the host 10 may receive the refresh information RFR_inf from the memory device 100 and control the refresh operation of the memory device 100 based on the refresh information RFR_inf.

In step S210, for the reference time, the memory device 100 counts the number of hidden refreshes and regular refreshes to generate a performance count, and generates refresh information based on the performance count. For example, as described in Figures 1-11, the refresh information may include a performance count, a hidden refresh execution count, or a refresh end flag.

At step S220, at the request of the host 10, the memory device 100 provides the host 10 with the refresh information RFR_inf. In step S230, the host 10 controls the refresh operation of the memory device 100 with respect to the reference time remaining based on the refresh information (RFR_inf). Step S230 will be described in detail with reference to FIG.

13 is a timing chart for explaining the operation of the electronic device of Fig. 1 according to the embodiment of the present invention. Fig. 13 will be described with reference to Figs. 1, 2 and 9. Fig. The definitions of the reference time, the refresh command REF, the valid command, the normal refresh execution period tREFI and the refresh execution time tRFC defined by the N normal refresh execution periods tREFI are the same as those described with reference to FIG. 9 same. Therefore, a description thereof will be omitted. In the example of FIG. 13, it is assumed that the refresh operation of the memory device 100 is performed at the end of the reference time when N normal refreshes are delayed (Postponed). Also, it is assumed that the request count (RFR_dnd) is N, as in Fig.

At t0 to t3, a plurality of hidden refreshes are performed in the memory device 100 together with the valid command (Valid). Thus, the refresh information RFR_inf is updated. At t4, the host 10 may provide a multipurpose register read command (MRR) to the memory device 100. The multipurpose register read command is defined by the JEDEC standard and may include an MRS (Mode Register Set) command and an address command. However, since this is not related to the present invention, a detailed description thereof will be omitted. In this way, the host 10 can be provided with the refresh information (RFR_inf) stored in the multipurpose register 195. Here, it is assumed that the memory device 100 performs the hidden refresh of M times t4. The host 10 may determine that M hidden refreshes have been performed in the memory device 100 based on the provided refresh information RFR_inf.

At t5 to t9, the host 10 can control the memory device 100 to perform the refresh of the number of times 'N-M + a'. In this case, the host 10 can control the memory device 100 to stop the hidden refresh operation at t5 to t9. The host 10 provides an effective command Valid to the memory device 100 during a time period (N-M + a) x tRFC 'required to perform the refresh operation of the number of times N-M + a' I never do that. In FIG. 13, '(N-M + a) x tRFC' time is shown as t5 to t9.

Here, 'a' is the number of times the refresh operation is performed for a special purpose, which is different from the hidden refresh and the regular refresh. 'a' may contain 0 and a natural number. That is, when 'a' is 0, the host 10 can control the memory device 100 to perform the regular refresh of the number of times 'N-M'. Alternatively, if 'a' is a natural number and the memory device 100 performs N times of hidden refresh during t0 to t5, the host 10 may determine that the memory device 100 is in the 'a' It is possible to control to additionally perform the refresh operation.

For example, to perform the refresh of the number of times 'N-M', the host 10 may provide the memory device 100 with the number of refresh commands REF 'N-M' times. In order to perform the refresh of the number of times 'a', the host 10 provides the memory device 100 with the refresh command REF for the number of times a, or the refresh command REF for the number of times a, A separate refresh command can be provided.

In other words, the host 10 is provided with the number of times of the hidden refresh execution, and provides the required number of refresh commands to the memory device 100, except for the number. In addition, the host 10 can control the memory device 100 to perform the refresh by the number of times of performing the refresh for a special purpose. Consequently, the host 10 can provide the valid command (Valid) to the memory device 100 for the time of the section " M X tRFC ", so that the efficiency of the command can be increased.

14 is a block diagram illustrating a memory device according to another embodiment of the present invention. 14, the memory device 200 includes a command decoder 210, an address latch 220, a memory cell array 230, a sense amplifier 231, a column decoder 240, an active controller 250, A controller 260, a row decoder 270, a data input driver 280, and a data output driver 290. The memory device 200 of FIG. 14 is identical to the memory device 100 of FIG. 2, except that it does not include a multipurpose register 195. Therefore, a description thereof will be omitted.

The memory device 200 of Fig. 14 includes a dedicated pad (RFR_inf) for providing the host 10 with refresh information (RFR_inf). Thus, the memory device 200 can provide the host 10 with the refresh information RFR_inf in real time. In this case, the host 10 may have a register for storing the provided refresh information (RFR_inf).

15 is a block diagram showing a stacked memory device to which a memory device according to another embodiment of the present invention is applied. 15, a stacked memory device 1000 may include a first and a second memory device 1100, 1200, a buffer die 1300, and a solder ball 1400. The number of stacked memory devices is not limited to that shown in Fig.

Each of the first and second memory devices 1100 and 1200 may include the memory devices 100 and 200 described with reference to Figs. Thus, each of the first and second memory devices 1100, 1200 may include refresh controllers 1160, 1260. Each of the refresh controllers 1160 and 1260 may include the refresh controllers 160 and 260 described with reference to FIGS. Each of the first and second memory devices 1100 and 1200 may be connected to each other by a TSV (Trough Silicon Via). Also, each of the first and second memory devices 1100, 1200 may be coupled to a buffer die 1300 by a Trough Silicon Via (TSV).

Buffer die 1300 may include a register 1360. The register 1360 may receive and store the respective refresh information from the first and second memory devices 1100 and 1200 connected by the TSV. Further, at the request of the host, the buffer die 1600 provides the refresh information stored in the register 1360 to the host through an input / output pad (not shown) and a solder ball (1400). Accordingly, the host can receive the refresh information for the first and second memory devices 1100 and 1200 by one command, thereby increasing the management efficiency of the refresh information.

In Fig. 15, as an example of the stacked memory device 1000, the structure of a memory device stacked by TSV is shown. However, the present invention is not limited thereto. It will be readily understood that the example of FIG. 15 can be applied to all memory types that can be stacked, such as a package on package (PoP) as well as a TSV.

16 and 17 are views showing a memory module according to another embodiment of the present invention.

The memory modules 2000 and 3000 shown in FIGS. 16 and 17 have a structure of a dual in-line memory module (DIMM) type. Each of the memory modules 2000 and 3000 may include a plurality of memory devices 100 and 200 described with reference to FIGS. 1 through 14, or the stacked memory device 1000 described with reference to FIG. However, for convenience of explanation, the first and second memory devices among a plurality of memory devices will be exemplarily described.

Referring to FIG. 16, an A-type memory module 2000 having the form of a Registered DIMM (RDIMM) is shown. The A-type memory module 2000 may include first and second memory devices 2100 and 2200, a command / address (CA) register 2300, and a refresh information transmission line 2400. The first and second memory devices 2100 and 2200 are connected to the CA register 2300. The CA register 2300 serves as a buffer for an address or command sent from the host to the first and second memory devices 2100 and 2200 to reduce the load on the host output.

In the structure of the RDIMM, when a host accesses the first and second memory devices 2100 and 2200, the host transmits data directly to the first and second memory devices 2100 and 2200 via the individual transmission line DQ_G Exchange. On the other hand, the host provides the address or command to the first and second memory devices 2100 and 2200 via the CA register 2300, respectively.

The CA register 2300 can receive and store the refresh information from the first and second memory devices 2100 and 2200 connected through the refresh information transmission line 2400, respectively. Further, at the request of the host, the CA register 2300 provides the stored refresh information to the host via the CA transmission line (CA). In this case, the CA transmission line CA will have directionality in both directions. Thus, since the host can receive refresh information for the first and second memory devices 2100 and 2200 by one command, management of the refresh information is facilitated.

 17, there is shown a B-type memory module 3000 having the form of a Load Reduced DIMM (LRDIMM). The B-type memory module 3000 may include first and second memory devices 3100 and 3200, a memory buffer 3300, and a transmission line 3400. The first and second memory devices 3100 and 3200 are connected to the memory buffer 3300 via a transmission line 3400. The memory buffer 3300 serves to reduce the load on the host output unit.

In the structure of the LRDIMM, when the host accesses the first and second memory devices 3100 and 3200, the host sends the data to the first and second memory devices 3100 and 3200 through the memory buffer 3300 and the transmission line 3400 ) And data, commands, and addresses indirectly.

The memory buffer 3300 can receive and store refresh information from the first and second memory devices 3100 and 3200 connected through the transmission line 3400, respectively. Further, at the request of the host, the memory buffer 3300 provides the stored refresh information to the host via the data transmission line (DATA). Thus, the host can receive the refresh information for the first and second memory devices 3100 and 3200 by one command, thereby facilitating management of the refresh information. As described above, the reset information (RFR_inf), the CA register 2300 of FIG. 16, and the stored value of the memory buffer 3300 of FIG. 17 are initialized by the reset command provided from the host aperiodically or periodically .

18 is a block diagram showing a user system to which a semiconductor memory device or a memory module according to an embodiment of the present invention is applied. The user system 4000 includes an image processing unit 4100, a wireless transmitting / receiving unit 4200, an audio processing unit 4300, an image file generating unit 4400, a memory 4500, a user interface 4600, and a controller 4700 .

The image processing unit 4100 may include a lens 4110, an image sensor 4120, an image processor 4130, and a display unit 4140. The wireless transceiver 4200 includes an antenna 4210, a transceiver 4220, and a modem 4230. The audio processing unit 4300 includes an audio processor 4310, a microphone 4320, and a speaker 4330.

The memory 4500 may be provided with a memory module (DIMM), a memory card (MMC, eMMC, SD, micro SD) or the like. In addition, the controller 4700 may be provided as a system-on-chip that drives application programs, operating systems, and the like. The controller 4700 may include an image processor 4130 or a modem 4230.

The memory 4500 may be provided to the memory devices 100, 200 including the refresh controllers 160, 260 described with reference to Figs. Alternatively, the memory 4500 may be provided as the stacked memory device 1000 described with reference to Fig. 15 or the memory modules 2000 and 3000 described with reference to Figs. 16 and 17. Fig. Therefore, the memory 4500 can provide the refresh information to the controller 4700, and the control of the refresh command can be performed efficiently by the controller 4700. [

The above description is a concrete example for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. In addition, the present invention includes techniques that can be easily modified by using the above-described embodiments.

1: electronic device 10: host
100, 200: memory device 110, 210: command decoder
120, 220: address latch 130, 230: memory cell array
131, 231: sense amplifier 140, 240: column decoder
150, 250: Active controller
160, 260, 1160, 1260: refresh controller
161: refresh address generator 162: address comparator
163, 163a, 163b, and 163c:
164: Oscillator 165: Refresh counter
166: Flag generator 170, 270: Low decoder
180, 280: Data input driver 190, 290: Data output driver
195: Multipurpose register
1000: stacked memory device
1100, 2100, 3100: a first memory device
1200, 2200, 3200: a second memory device
1300: logic die 1400: solder ball
2000, 3000: memory module 2300: CA register
2400: Refresh transmission line 3300: Memory buffer
3400: transmission line 4000: user system
4100: image processing unit 4110: lens
4120: image sensor 4130: image processor
4140: Display 4200: Wireless Transmission /
4210: Antenna 4220: Transceiver
4230: modem 4300: audio processor
4310: Audio Processor 4320: Microphone
4330: Speaker

Claims (20)

A memory cell array;
A refresh controller for performing a hidden refresh performed without an instruction of a host or a normal refresh performed by a refresh command of the host on the memory cell array; And
And a refresh information generator for counting the hidden refresh and the number of times of performing the normal refresh to generate a performance count and generating refresh information based on the performance count. The method of claim 1,
Wherein the memory cell array includes first and second banks,
Wherein the refresh controller includes a first refresh controller for the first bank and a second refresh controller for the second bank,
Wherein the refresh information generator includes a first refresh information generator for the first refresh controller and a second refresh information generator for the second refresh controller. The method of claim 1,
And a dedicated pad for providing the execution count or the refresh information to the host. The method of claim 1,
Further comprising a register for storing the execution count or the refresh information,
Wherein the stored execution count or the refresh information is provided to the host at the request of the host. 5. The method of claim 4,
Wherein the register is reset upon request from the host. The method of claim 1,
The refresh controller includes:
An address generator for generating a row address in the memory cell array to be refreshed;
A comparator for comparing the generated row address with a row address of an access address, and generating a hidden refresh active signal for performing the hidden refresh according to a result of the comparison; And
And logic sum (OR) logic for generating a refresh signal by logically summing the normal refresh active signal and the hidden refresh active signal for performing the normal refresh,
Wherein the access address is an address for performing a read or a write command within the memory cell array. The method of claim 1,
The refresh information generator includes:
A counter for updating the count at every regular refresh execution cycle to generate a regular refresh cycle count; And
And a comparator that compares the normal refresh cycle count with the performance count and generates the refresh information based on the comparison result. 8. The method of claim 7,
Wherein the refresh information comprises a performance count of the hidden refresh generated based on the performance count or the comparison result,
Wherein the performance count or refresh information is provided to the host upon request of the host. The method of claim 1,
Wherein the refresh information generator is provided with a refresh request count, generates the refresh information based on the refresh request count and the execution count,
Wherein the refresh request count is the number of refreshes to be performed for the memory cell array for a reference time. The method according to claim 9,
Wherein the refresh information includes a refresh end flag generated when the performance count is equal to or greater than the refresh request count,
Wherein the refresh end flag is provided to the host within a predetermined period of time after a request for the host is made or a request for the host is not made after the refresh end flag is generated. The method of claim 1,
Wherein the execution count and the refresh information are reset at the request of the host. In the refresh information providing method of the volatile memory device performing the hidden refresh or the regular refresh,
Performing the hidden refresh or the normal refresh in the volatile memory device;
Counting the number of hidden refreshes and the number of regular refreshes to generate a performance count, and generating refresh information based on the performance count; And
And providing the execution count or the refresh information to the host. 13. The method of claim 12,
Wherein the refresh information is a refresh count including a refresh end flag generated when the execution count and the execution count are equal to or greater than the refresh request count. 14. The method of claim 13,
Wherein the providing step provides the refresh end flag to the host within a predetermined time if there is a request from the host after the refresh end flag is generated or there is no request from the host. 13. The method of claim 12,
Wherein the providing step provides the execution count or the refresh information to the host at the request of the host. 13. The method of claim 12,
Wherein the execution count and the refresh information are reset at a request of the host. In a refresh control method of an electronic device including a volatile memory device performing a hidden refresh or a regular refresh during a reference time and a host controlling a refresh operation of the volatile memory device,
Counting the number of times of the hidden refresh and the normal refresh performed in the volatile memory device to generate a performance count, and generating refresh information based on the performance count;
Providing the execution count or the refresh information to the host at the request of the host; And
And controlling, by the host, a refresh operation of the volatile memory device with respect to a reference time remaining based on the execution count or the refresh information. 18. The method of claim 17,
The step of controlling the refresh operation includes:
And the host controls the volatile memory device to perform a refresh operation as many times as the necessary number of times of refresh refresh execution in the refresh request count with respect to the remaining reference time. 19. The method of claim 18,
The step of controlling the refresh operation includes:
And the host controls the volatile memory device to perform a refresh operation for the remaining reference time in the required number of times by the number of special refreshes. 20. The method of claim 19,
Wherein the special refresh is performed by a command different from the normal refresh and the refresh for the necessary number of times.

Images