KR20160105369A - A light emitting diode - Google Patents

Abstract

A lower semiconductor layer formed on a substrate; An upper semiconductor layer disposed on the lower semiconductor layer such that at least a part of edge regions of the lower semiconductor layer are exposed; A first electrode formed on a part of the upper semiconductor layer to supply current to the lower semiconductor layer through an insulating layer; A second electrode formed on another portion of the upper semiconductor layer to supply current to the upper semiconductor layer; And an extension of the first electrode extending from the first electrode to reach at least a part of the exposed lower semiconductor layer.

Description

A light emitting diode

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting diode, and more particularly, to a light emitting diode capable of reducing a reduction in a light emitting area by an electrode or an electrode pad.

Gallium nitride (GaN) series light emitting diodes have been applied and developed for about 10 years or more. GaN-based LEDs have significantly changed LED technology and are currently used in a variety of applications including color LED display devices, LED traffic signals, and white LEDs. In recent years, high efficiency white LEDs are expected to replace fluorescent lamps. In particular, the efficiency of white LEDs has reached a level similar to that of ordinary fluorescent lamps.

Gallium nitride based light emitting diodes are generally formed by growing epitaxial layers on a substrate such as sapphire and include an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed therebetween. On the other hand, an N-electrode is formed on the N-type semiconductor layer, and a P-electrode is formed on the P-type semiconductor layer. The light emitting diode is electrically connected to an external power source through the electrodes. At this time, current flows from the P-electrode to the N-electrode through the semiconductor layers.

Generally, since the P-type semiconductor layer has a high resistivity, the current is not uniformly dispersed in the P-type semiconductor layer, the current is concentrated in the portion where the P-electrode is formed, and current flows intensively through the edge do. The current concentration leads to reduction of the light emitting region, and as a result, the luminous efficiency is lowered. In order to solve such a problem, a technique of forming a transparent electrode layer having a low specific resistance on the P-type semiconductor layer to achieve current dispersion is used. The current flowing from the P-electrode is dispersed in the transparent electrode layer and flows into the P-type semiconductor layer, so that the light emitting region of the light emitting diode can be widened.

However, since the transparent electrode layer absorbs light, its thickness is limited, and therefore current dispersion is limited. In particular, current dispersion using a transparent electrode layer is limited in a large area light emitting diode of about 1 mm 2 or more, which is used for high output.

On the other hand, the current flows through the semiconductor layers and exits to the N-electrode. Accordingly, a current is concentrated at a portion where the N-electrode is formed in the N-type semiconductor layer, which means that a current flowing in the semiconductor layer is concentrated near the region where the N-electrode is formed. Therefore, a light emitting diode capable of improving current concentration in the N-type semiconductor layer is also required.

Typically, a diagonal electrode structure shown in FIG. 1 and a facing structure + symmetry extending structure shown in FIG. 2 are introduced for uniform current spreading in a light emitting diode.

FIG. 1 is a view for explaining a light emitting diode having a conventional diagonal electrode structure, FIG. 2 is a view for explaining a conventional light emitting diode having a face structure and a symmetric expandable electrode structure, FIG. 3 is a cross- A-A '. 1, reference numeral 1 denotes an N-type electrode, 2 denotes a P-type electrode, 3 denotes an exposed N-type semiconductor layer, and 4 denotes a transparent electrode layer. In FIGS. 2 and 3, reference numeral 11 denotes a substrate, 13 denotes an N-type semiconductor layer, 15 denotes an active layer, 17 denotes a P-type semiconductor layer, 19 denotes a transparent electrode layer, and 22 and 23 denote extensions.

Referring to FIG. 1, the diagonal electrode structure can exhibit a large effect in a light emitting diode having a small size. However, as the area of the light emitting diode increases, the current concentration phenomenon is strengthened at the center, Lt; / RTI > Also, the electrode pattern of a simple face-to-face structure has the same problems as the diagonal electrode structure.

On the other hand, as the size of the LED chip becomes larger, an extended portion of the electrode spreads over the entire light emitting area for a uniform current distribution over a larger light emitting area. For example, referring to FIGS. 2 and 3, the conventional face-to-face structure + symmetry extension structure is mainly used for a large-sized LED, but the extension portions 32 and 33 of the P- And the N-type semiconductor layer 13 must be exposed by mesa etching in order to form the extended portions 22 and 23 of the N electrode 21 and the N-type semiconductor layer 13, there is a problem that a sacrifice in which the light emitting area is reduced is inevitable.

In addition, there is a trend of increasing the number of electrode pads formed on one chip for current diffusion to two or more, and the mesa etching area for forming the extended portion from the electrode and the electrode is also enlarged. The enlargement of the mesa etching area due to the increase of the pads reduces the light emitting area on the basis of the same chip area and lowers the light emitting efficiency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode capable of reducing a decrease in the light emitting area due to electrodes or electrode pads.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a lower semiconductor layer formed on a substrate; An upper semiconductor layer disposed on the lower semiconductor layer such that at least a part of edge regions of the lower semiconductor layer are exposed; A first electrode formed on a part of the upper semiconductor layer to supply current to the lower semiconductor layer through an insulating layer; A second electrode formed on another portion of the upper semiconductor layer to supply current to the upper semiconductor layer; And an extension of a first electrode extending from the first electrode to reach at least a part of the exposed lower semiconductor layer is provided

The insulating layer may be formed entirely on the upper semiconductor layer.

The insulating layer may include an insulating layer having a DBR structure formed under the portion where the first electrode is formed.

The light emitting diode may further include an insulating layer having a DBR structure formed at a lower portion of the extended portion of the first electrode in a mesa surface region formed so as to expose at least a part of edge regions of the lower semiconductor layer.

The light emitting diode may further include an insulating layer of a DBR structure formed around an extension of the first electrode formed to reach at least a part of the exposed lower semiconductor layer.

The light emitting diode may further include an insulation layer having a DBR structure formed under the second electrode.

The extended portion of the first electrode may be formed on an inclined mesa surface extending from the upper semiconductor layer to the lower semiconductor layer.

The light emitting diode may further include an extension of a second electrode formed on the upper semiconductor layer and extending from the second electrode.

The substrate may further include an insulating layer having a DBR structure.

The light emitting diode may further include a transparent electrode layer formed on the upper semiconductor layer.

According to the present invention, in forming an electrode and an extension for supplying a current to a lower semiconductor layer, an area of the semiconductor layer removed by mesa etching in order to form an electrode and an extension part on the upper semiconductor layer via an insulating layer Is relatively reduced as compared with the related art, and the reduction of the light emitting area can be reduced.

1 is a view for explaining a light emitting diode having a conventional diagonal electrode structure.
2 is a view for explaining a light emitting diode having a conventional face-to-face structure and a symmetric expandable electrode structure.
3 is a cross-sectional view taken along the tear line AA of FIG.
4 is a plan view illustrating a light emitting diode according to an embodiment of the present invention.
5 is a cross-sectional view taken along the tear line AA in Fig.
6 is a plan view illustrating a light emitting diode according to another embodiment of the present invention.
7 is a cross-sectional view taken along the percutaneous line B-B 'of Fig. 6
8 is a cross-sectional view taken along a perforated line C-C 'in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples for allowing a person skilled in the art to sufficiently convey the idea of the present invention. Therefore, it is to be understood that the present invention is not limited to the embodiments described below, but may be embodied in other forms.

FIG. 4 is a plan view for explaining a light emitting diode according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the cutting line A-A in FIG.

Referring to FIGS. 4 and 5, a first conductive type lower semiconductor layer 113 is disposed on a substrate 111. The substrate 111 is not particularly limited and may be a sapphire substrate.

A second conductive upper semiconductor layer 117 is disposed on the first conductive lower semiconductor layer 113. The upper semiconductor layer 117 is located in a region surrounded by edges of the lower semiconductor layer 113 such that at least a part of the edge regions of the lower semiconductor layer 113 are exposed. Meanwhile, an active layer 115 is interposed between the lower semiconductor layer 113 and the upper semiconductor layer 117. The active layer 115 is located under the upper semiconductor layer 117 so that at least a portion of the edge regions of the lower semiconductor layer 113 are still exposed.

The lower semiconductor layer 113, the active layer 115 and the upper semiconductor layer 117 may be formed of a gallium nitride compound semiconductor material, that is, (B, Al, In, Ga) N, but the present invention is not limited thereto . The composition of the lower semiconductor layer 113 and the upper semiconductor layer 117 is determined so that the active layer 115 emits light of a desired wavelength such as ultraviolet or blue light. Is formed of a large material.

The lower semiconductor layer 113 and / or the upper semiconductor layer 117 may be formed as a single layer as shown in FIG. In addition, the active layer 115 may have a single quantum well structure or a multiple quantum well structure. A buffer layer (not shown) may be interposed between the substrate 111 and the lower semiconductor layer 113. The buffer layer is adopted to alleviate the lattice mismatch between the substrate 111 and the lower semiconductor layer 113 to be formed thereon.

The semiconductor layers 113, 115, and 117 may be formed using MOCVD or MBE techniques, and mesa etching may be performed to expose regions of the lower semiconductor layer 113 using photolithography and etching processes .

At this time, in the mesa etching, it is preferable that the mesa surface of the semiconductor layer by the mesa etching be inclined. The mesa surface may have an inclination of, for example, 20 to 80 degrees, and more preferably, an inclination of 30 to 60 degrees.

When the mesa etching surface is formed to be inclined, workability and reliability can be improved in forming the DBR layer 140 and the first electrode inclined extension 122 to be performed later. Further, the effect of widening the light emitting area is obtained.

An insulating layer is formed on the upper semiconductor layer 117. The insulating layer may include a first insulating layer 119 and a second insulating layer 140. The first insulating layer 119 is formed entirely on the upper semiconductor layer 117 and the inclined plane formed by the mesa etching. For example, SiO ₂ , Si ₃ N ₄ , and TiO ₂ may be used.

The second insulating layer 140 may be formed such that the inclined extension 122 of the first electrode 121 is formed in a region of the upper semiconductor layer 117 where the first electrode 121 is to be formed and a mesa- As shown in FIG.

The second insulating layer 140 may be a DBR structure layer, for example, a material having a large refractive index difference.

The DBR (Distributed Bragg Reflector) structure layer is used when a high reflectance is required in various light emitting devices including a light emitting function, an optical detecting function, and a light modulating function. The DBR structure layer can alternately laminate two kinds of media having different refractive indexes, and can perform a function of reflecting light by using a difference in refractive index.

The second insulating layer 140 is formed by alternately stacking two or more insulating layers having different refractive indices. For example, the second insulating layer 140 may be formed by alternately stacking SiO ₂ and TiO ₂ , or alternately stacking SiO ₂ and Si ₃ N ₄ into a plurality of layers. Then, the second insulating layer 140 may be formed using a photolithography technique, May be formed by patterning etching.

The second insulating layer 140 may be formed by stacking a plurality of insulating layers having different refractive indexes in a plurality of layers alternately so as to function as a DBR (Distributed Bragg Reflector) The light generated by the active layer 117 can be effectively absorbed or blocked by the first electrode 121 by reflecting the light when proceeding to the first electrode 121.

The second insulating layer 140 of the DBR structure may be formed not only on the lower portion of the first electrode 131 but also on a portion of the lower portion of the second electrode 131 except for a portion contacting the upper semiconductor layer 117 There is also.

May be formed in the exposed lower semiconductor layer 113 to increase the extraction efficiency of the light reflected by the lower portion of the first electrode 121 or the second insulating layer 140 formed on the mesa surface. The DBR layer 111b may be formed on the upper PSS region 111a of the substrate 111 or may be formed on the bottom of the substrate 111 (not shown).

A first electrode 121 is formed on a portion of a first region on the upper semiconductor layer 117 with a first insulating layer 119 and a second insulating layer 140 interposed therebetween, A first electrode inclined extension portion 122 and a first electrode lower extension portion 123 extending from the first electrode 121 to the edge region of the exposed lower semiconductor layer 113 are formed. The first electrode 121, the first electrode tapered extension portion 122, and the first electrode lower extension portion 123 may be formed together through the same material and the same process. For example, when the lower semiconductor layer is N-type, the first electrode 121, the first electrode tapered extension portion 122, and the first electrode lower extension portion 123 may be formed of Ti / Al using a lift- .

In addition, a second electrode 131 is formed in a second region of the upper semiconductor layer 117. The second electrode 131 is located on the upper semiconductor layer 117 at a corner between a second side adjacent to the first side and a third side adjacent to the second side.

A transparent electrode layer (not shown) may be formed on the upper semiconductor layer 117 before the first insulating layer 119 is formed. In general, the transparent electrode layer is formed of ITO or Ni / Au to have a light-transmitting property, and may be ohmic-contacted to the upper semiconductor layer 117 to lower the contact resistance. However, the second electrode 131 does not have a light-transmitting property and is not ohmic-contacted to the upper semiconductor layer. Therefore, by bringing the second electrode 131 directly into contact with the upper semiconductor layer 117, it is possible to prevent a current from flowing under the second electrode 131, and the generated light is transmitted to the second electrode 131 And can be prevented from being absorbed and lost.

On the other hand, a first extension 132 of the second electrode extends from the second electrode 131 and is formed on the upper semiconductor layer 117 adjacent to the second side, and the second extension 132 of the second electrode (133) extends from the second electrode (131) and is formed adjacent to the third side. The second electrode 131, the first extension 132 of the second electrode, and the second extension 133 of the second electrode may be formed of the same material and the same process.

2 and 4, a comparison is made with respect to the area of the light emitting area in the light emitting diode according to one embodiment of the present invention and the light emitting diode according to the related art.

2 and FIG. 4, it can be seen that there is a large difference in the area of the light emitting region reduced by the lower electrode 21 and the first electrode 121 for supplying current to the lower semiconductor layer. That is, in FIG. 2, the light emitting region including the active layer 15 corresponding to the area of the lower electrode 21 is removed by mesa etching. 4, the first electrode 121 is formed on the upper semiconductor layer 117 via the first insulating layer 119 and the second insulating layer 140, and the active layer 115 remains as it is. Therefore, it is possible to effectively solve the reduction of the light emitting area conventionally.

4, the light that can be absorbed or shielded by the first electrode 121 can be efficiently reflected by the second insulating layer 140 having the DBR structure formed under the first electrode 121 And can be discharged to the outside.

6 is a plan view for explaining a light emitting diode according to another embodiment of the present invention, FIG. 7 is a sectional view taken along the cut line B-B 'in FIG. 6, and FIG. 8 is a cross sectional view taken along the cut line C- Fig.

4 and 5, the number, position, and shape of the first electrode and the second electrode have been modified, and the extension of the first electrode and the second electrode have been modified in the following embodiments of the present invention, And the shape of the extended portion of the second electrode are deformed.

6, 7, and 8, the first electrodes 221 and 224 are formed on the upper semiconductor layer 217 such that the second electrodes 231 and 234 face each other, and the extension of the first electrode The electrodes 223 and 225 are formed between the extensions 232, 233 and 235 of the second electrode and are formed corresponding to each other.

The first conductive type lower semiconductor layer 213 is located on the substrate 211. The substrate 211 is not particularly limited and may be a sapphire substrate.

A second conductive upper semiconductor layer 217 is disposed on the first conductive lower semiconductor layer 213. The upper semiconductor layer 217 is located in a region surrounded by the edges of the lower semiconductor layer 213 such that at least a part of the edge regions of the lower semiconductor layer 213 are exposed. Meanwhile, an active layer 215 is interposed between the lower semiconductor layer 213 and the upper semiconductor layer 217. The active layer 215 is located under the upper semiconductor layer 217 so that at least a part of the lower semiconductor layer 213 is still exposed.

The lower semiconductor layer 213, the active layer 215 and the upper semiconductor layer 217 may be formed of a gallium nitride compound semiconductor material, that is, (B, Al, In, Ga) N, but the present invention is not limited thereto . The composition of the lower semiconductor layer 213 and the upper semiconductor layer 217 is determined so that the active layer 215 emits light having a desired wavelength such as ultraviolet or blue light. Is formed of a large material.

The lower semiconductor layer 213 and / or the upper semiconductor layer 217 may be formed as a single layer or may have a multi-layer structure as shown in the figure. In addition, the active layer 215 may have a single quantum well structure or a multiple quantum well structure. A buffer layer (not shown) may be interposed between the substrate 211 and the lower semiconductor layer 213. The buffer layer is adopted to alleviate the lattice mismatch between the substrate 211 and the lower semiconductor layer 213 to be formed thereon.

The semiconductor layers 213, 215, and 217 may be formed using MOCVD or MBE techniques, and mesa etching may be performed to expose regions of the lower semiconductor layer 213 using a photolithography process and an etching process .

At this time, in the mesa etching, it is preferable that the mesa surface of the semiconductor layer by the mesa etching be inclined. The mesa surface may have an inclination of, for example, 20 to 80 degrees, and more preferably, an inclination of 30 to 60 degrees.

When the mesa etching surface is formed to be inclined, workability and reliability can be improved in forming the DBR layer 240 and the first electrode inclined extension portion 222 to be performed later. Further, the effect of widening the light emitting area is obtained.

An insulating layer is formed on the upper semiconductor layer 217. The insulating layer may include a first insulating layer 219 and a second insulating layer 240. The first insulating layer 219 is formed entirely on the upper semiconductor layer 217 and the inclined plane formed by the mesa etching. For example, SiO ₂ , Si ₃ N ₄ , and TiO ₂ may be used.

The second insulating layer 240 may be formed on the upper semiconductor layer 217 in the regions where the first electrodes 221 and 224 are to be formed and the mesa surfaces by mesa etching, 225 may be formed.

The second insulating layer 240 may be a DBR structure layer, for example, a material having a large refractive index difference.

The DBR (Distributed Bragg Reflector) structure layer is used when a high reflectance is required in various light emitting devices including a light emitting function, an optical detecting function, and a light modulating function. The DBR layer can alternately laminate two kinds of media having different refractive indexes, and can perform a function of reflecting light by using the difference in refractive index.

The second insulating layer 240 is formed by alternately stacking two or more insulating layers having different refractive indices. The second insulating layer 240 may be formed by alternately stacking SiO ₂ and TiO ₂ , or alternately stacking SiO ₂ and Si ₃ N ₄ into a plurality of layers. Then, using the photolithography technique, May be formed by patterning etching.

The second insulating layer 240 functions as a DBR (Distributed Bragg Reflector) because two or more insulating layers having different refractive indexes are alternately stacked to form a plurality of layers. Light generated in the active layer 217 is transmitted to the first electrode The light generated from the active layer 217 can be effectively absorbed or blocked by the first electrodes 221 and 224 by reflecting the light when proceeding to the first and second electrodes 221 and 224.

The second insulating layer 240 of the DBR structure includes not only the lower part of the first electrodes 221 and 224 but also the lower part of the second electrodes 231 and 234 except for the portion contacting the upper semiconductor layer 217 As shown in Fig.

May be formed in the exposed lower semiconductor layer 213 to increase the extraction efficiency of light reflected by the second insulating layer 240 formed on the lower or mesa surfaces of the first electrodes 221 and 224 . The DBR layer 211b may be formed on the upper PSS region 211a of the substrate 211 or may be formed on the bottom of the substrate 211 (not shown).

First electrodes 221 and 224 are formed on a portion of a first region on the upper semiconductor layer 217 with a first insulating layer 219 and a second insulating layer 240 interposed therebetween. (223, 225) of the first electrode extending from the exposed lower semiconductor layer (213). The first electrodes 221 and 224 and the extensions 223 and 225 of the first electrode may be formed together through the same material and the same process. For example, when the lower semiconductor layer is N-type, the first electrodes 121 and 224 and the extensions 223 and 225 of the first electrode may be formed of Ti / Al using a lift-off technique.

Second electrodes 231 and 234 are formed in a second region of the upper semiconductor layer 217. The second electrodes 231 and 234 are positioned on the upper semiconductor layer 217 at appropriate intervals on the edge of the second side opposite to the first side.

A transparent electrode layer (not shown) may be formed on the upper semiconductor layer 217 before the first insulating layer 219 is formed. In general, the transparent electrode layer is formed of ITO or Ni / Au to have light-transmitting property, and may be ohmic-contacted with the upper semiconductor layer 217 to lower the contact resistance. However, the second electrodes 231 and 234 do not have translucency and are not ohmic-contacted to the upper semiconductor layer. Therefore, by bringing the second electrodes 231 and 234 directly into contact with the upper semiconductor layer 217, current can be prevented from flowing under the second electrodes 231 and 234, (231, 234) and can be prevented from being lost.

On the other hand, a first extended portion 232 of the second electrode extends from the second electrode 231 and is formed on the upper semiconductor layer 217 adjacent to the third side, and the second extended portion 232 of the second electrode (233) extending from an intermediate portion of the second electrodes (231, 234) to an intermediate portion of the substrate. A third extended portion 235 of the second electrode is formed on the upper semiconductor layer 217 at a fourth side extending from the second electrode 234 and facing the third side. The second electrodes 231 and 234, the first extension 232 of the second electrode, the second extension 233, and the third extension 235 may be formed of the same material and the same process .

2 and 6, a comparison is made with respect to the area of the light emitting area in the light emitting diode according to one embodiment of the present invention and the light emitting diode according to the related art.

2 and 6, it can be seen that there is a large difference in the area of the light emitting region reduced by the lower electrode 21 and the first electrodes 221 and 224 for supplying current to the lower semiconductor layer. That is, in FIG. 2, the light emitting region including the active layer 15 corresponding to the area of the lower electrode 21 is removed by mesa etching. Of course, although one lower electrode 21 is formed in FIG. 2, if two lower electrodes 21 are formed according to FIG. 6, the number of the light emitting regions removed by the mesa etching becomes much larger. 6, the first electrodes 221 and 224 are formed on the upper semiconductor layer 217 via the first insulating layer 219 and the second insulating layer 240 and the active layer 215 is left as it is have. Therefore, it is possible to effectively solve the reduction of the light emitting area conventionally.

6 and 8, the first electrode 221 and the second electrode 224 are absorbed by the second electrodes 221 and 224 by the second insulating layer 240 having the DBR structure formed under the first electrodes 221 and 224 Light that can be blocked can be effectively emitted to the outside.

Although several embodiments of the present invention have been illustrated by way of example, those skilled in the art will appreciate that various modifications and changes may be made without departing from the essential characteristics of the present invention. Therefore, it should be understood that the above-described embodiments are not intended to limit the scope of the present invention, but merely to facilitate a better understanding thereof. The scope of the present invention is not to be limited by these embodiments, but should be construed according to the following claims, and equivalents thereof are to be construed as being included in the scope of the present invention.

Claims (13)

A lower semiconductor layer;
An upper semiconductor layer disposed on the lower semiconductor layer such that at least a part of edge regions of the lower semiconductor layer are exposed;
A first electrode disposed on the upper semiconductor layer and supplying current to the lower semiconductor layer;
A first electrode extension portion extending from the first electrode and including a first electrode tapered extension portion located on a side inclined surface of the upper semiconductor layer and a first electrode lower extension portion located on the exposed lower semiconductor layer;
An insulating layer having a DBR structure interposed between the first electrode and the first electrode inclined extension and the upper semiconductor layer; And
And a first insulating layer interposed between the insulating layer of the DBR structure and the upper semiconductor layer. The method according to claim 1,
Wherein the first electrode, the first electrode inclined extension, and the first electrode lower extension comprise Al layers. The method according to claim 1,
Wherein the insulating layer of the DBR structure extends to the exposed region of the lower semiconductor layer on the upper semiconductor layer. The method according to any one of claims 1 to 3,
The first insulating layer is a light emitting diode is selected from the group consisting of _{SiO 2, Si 3 N 4,} TiO 2. The method according to claim 1,
Wherein the insulating layer of the DBR structure and the first insulating layer partially overlap each other. The method according to any one of claims 1 to 3,
And a second electrode disposed on the upper semiconductor layer for supplying current to the upper semiconductor layer. The method of claim 6,
The insulating layer of the DBR structure is also disposed under the second electrode,
And the second electrode is electrically connected to the upper semiconductor layer through the insulating layer of the DBR structure. The method according to any one of claims 1 to 3,
And an ohmic contact layer for ohmic contact with the upper semiconductor layer, wherein the second electrode is connected to the ohmic contact layer. The method of claim 8,
Wherein the ohmic contact layer includes a transparent electrode layer. The method according to any one of claims 1 to 3,
And a substrate on which the lower semiconductor layer is disposed,
Wherein the substrate comprises an insulating layer of a DBR structure. The method according to any one of claims 1 to 3,
Wherein the upper semiconductor layer is located in a region surrounded by an edge of the lower semiconductor layer. The method of claim 11,
Wherein the upper semiconductor layer has an inclined mesa surface, wherein the mesa surface has an inclination of 20 to 80 degrees. The method according to any one of claims 1 to 3,
And an active layer interposed between the lower semiconductor layer and the upper semiconductor layer.

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