KR20150057382A - eFuse OTP Memory device with Differnetial Paired - Google Patents

Abstract

The present invention relates to a differential pair structure eFuse OTP memory device. The present invention provides a cell array comprising at least one OTP memory cell; And an IRD control circuit for, when a program pulse supplied to the OTP memory cell is output in accordance with a read signal in a read mode, a glitch pulse is generated in the read signal, The IRD control circuit enables the currently performed read mode to be continuously performed when the read signal is in a high state, thereby providing a power IC chip resistant to noise such as a glitch pulse. Further, when the sensing operation for the bit line BL is completed in the e-fuse OTP memory device, the second NMOS and the fourth NMOS provided for the read mode are turned off, Thereby preventing blowing by the development.

Description

[0001] The present invention relates to an e-fuse OTP memory device with differential pair structure,

The present invention relates to an OTP memory device, and more particularly, to an OTP memory device that reduces a noise immunity to a glitch pulse generated in a read signal (RD) port during a power on time of a power IC chip, Fuse OTP memory device in which a fuse link is prevented from being blown by electromigration (EM) phenomenon. .

The power IC chip requires a small amount of nonvolatile memory to perform the analog trimming function. Non-volatile memories include devices such as EPROM, EEPROM, and flash memory. However, these non-volatile memories require additional processes that result in longer turn-around times (TAT), increased complexity, lower reliability and higher manufacturing costs.

Therefore, OTP (One-Time Programmable) memory devices capable of designing an eFuse or an anti-Fuse logic process that does not require an additional process are widely used. Recently, an e-fuse type OTP memory device is widely used.

The memory capacity of the fuse OTP memory device is required to be several tens of bits or less. The program is performed by blowing the fuse link in the same manner as the electromigration (EM) phenomenon and the thermal rupture by flowing an overcurrent of about 10 mA to 20 mA to the fuse. In this case, the fuse has a pre-program resistance of about 50 to 100 Ω, and when the data is programmed with program overcurrent flowing through the fuse link, the fuse is more than several tens of kΩ.

Meanwhile, when the external power supply voltage is higher than a predetermined level (for example, about 1.7 V or more) during a power-up operation, the power IC chip on which the eFuse memory device is mounted has a reset (RST) The high state is switched to the low state. Then, the power IC chip reads the program data stored in the eFuse memory device and performs a trimming operation on the analog circuit.

However, a power IC chip equipped with a common e-fuse OTP memory device has the following problems.

First, due to a large switching current, a power IC chip generates unnecessary glitch pulses in a read signal (RD) due to reasons such as power or ground noise. When the glitch pulse is generated, the power IC chip can not normally perform the read mode. This means that the power IC chip can not normally read the program data stored in the memory cell of the eFuse memory device. Therefore, the power IC chip is forced to output the failed data, and the desired trimming operation can not be performed on the analog circuit. Therefore, in order to improve the operation reliability of the power IC chip, a high noise immunity-sensitive eFuse OTP memory device such as a glitch pulse was required.

Also, in the case of a transistor for a read mode provided in the fuse OTP memory device, a DC current of several tens of microamperes often flows, which causes undesirable breakdown of the fuse link by EM phenomenon. This results in errors in the output data.

Further, after the power IC chip is packaged, an electrical characteristic change may occur in an internal circuit. In this case, the performance of the power IC chip becomes poor, and normal operation becomes difficult. Therefore, the data must be programmable even after the power IC chip is packaged.

Korean Patent Publication No. 2012-0131470, a reading circuit of an OTP memory U.S. Published Patent 2009-0251943, Test circuit for an unprogrammed OTP memory array

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a differential pair type eFuse memory device having a strong noise immunity to a glitch pulse generated in a read signal in a read mode of a power IC chip.

Another object of the present invention is to prevent the fuse link from being blown by the EM phenomenon.

Another object of the present invention is to enable data to be programmed even when the power IC chip is packaged.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a cell array including at least one OTP memory cell; And an IRD control circuit for, when a program pulse supplied to the OTP memory cell is output in accordance with a read signal in a read mode, a read mode is not performed when a glitch pulse is generated in the read signal, Lt; RTI ID = 0.0 > OTP < / RTI > memory device.

The IRD control circuit outputs an IRD signal so that the current read mode is continuously performed when the read signal is in a high state.

Even if the read signal goes low, the IRD signal keeps the high state so that the data output by the read signal remains unchanged.

When the IRD signal changes from a low state to a high state, the read mode is performed, and the read mode continues until the power of the IC chip is down.

The IC chip includes the eFuse OTP memory device.

The IRD control circuit includes: a first inverter receiving a read (RD) signal; A second NAND receiving an output of the first inverter and an output of the first NAND; A third NAND receiving an output of the second NAND and an IRSTb signal; And a fourth NAND for receiving an output of the third NAND and a read (RD) signal inverted through a second inverter and outputting an IRD signal, wherein the first NAND gate receives the IRSTb signal and the second NAND gate And apply a logic-computed signal to the input signal of the second NAND gate.

The eFuse memory device of the present invention includes a first NMOS and a second NMOS connected in series; A first eFuse connected to the connection node of the first NMOS and the second NMOS; A third NMOS and a fourth NMOS connected in series; A second eFuse connected to the connection node of the third NMOS and the fourth NMOS; A read word line (RWL) coupled to the gates of the second NMOS and the fourth NMOS; And a sense amplifier sensing a differential voltage between the bit line BL and the bit line BLb when the voltage of the bit line BL (BLb) is pulled up by the variable pull-up load circuit, When the sensing operation is completed, the second NMOS and the fourth NMOS are turned off.

When the second NMOS and the fourth NMOS are turned off, the DC current is cut off.

In the DC current cutoff, a driving method of applying a pulse to the word line WL is used.

The variable pull-up load circuit performs a sensing margin test and varies the impedance of the full-up load of the bit line pre-charge circuit used in the program verify read mode and the read mode.

According to the eIFT memory device of the differential pair structure of the present invention, the following effects can be obtained.

First, the fuse OTP memory device provides a noise-resistant IRD control circuit such as a glitch pulse. The IRD control circuit prevents the read mode from entering again when a glitch pulse is generated in the read signal in the read mode. Thus, the read data remains unchanged, and a power IC chip resistant to noise such as a glitch pulse is provided can do.

Further, it is possible to prevent the fuse link from being blown by the EM phenomenon, thereby improving the reliability of the fuse OTP memory device.

Since the data can be programmed even in the state where the power IC chip is packaged, the effect of coping with the change in the electrical characteristics of the power IC chip can be expected.

1 is a block diagram of an eFuse OTP memory device according to an embodiment of the present invention;
Fig. 2 is a circuit diagram showing a fuse cell in which a differential pair, which is a unit memory cell constituting the cell array 140 of Fig. 1,
Fig. 3 is a circuit diagram of a cell array of 1 row x 8 columns constituting the cell array of Fig. 1
Figures 4A and 4B are timing diagrams in which the eFuse OTP memory device of Figure 1 operates in a program mode and a read mode
FIG. 5 is a diagram showing a variable pull-up load circuit configuration for performing a sensing margin test in consideration of fluctuations of the eFuse resistance programmed in the cell array shown in FIG.
6A and 6B are circuit diagrams for sensing and outputting a differential voltage between the bit lines BL and BLb
Fig. 7 is a circuit diagram of the comparator shown in Fig.
8 is a timing diagram when the eFuse OTP memory device according to the embodiment of the present invention operates in the program verification read mode
9 is an IRD control circuit configuration diagram provided in an eFuse OTP memory device in accordance with an embodiment of the present invention.
10 is a control timing diagram of the eFuse OTP memory device of the present invention
11 is a block diagram of the SL switching circuit provided in the eFuse memory device of the present invention
12 is an experimental result of the program verification read mode according to the embodiment of the present invention. In FIG. 12, (a) shows a case where the program is programmed as '1'
Figure 13 is an image plot showing the layout of an 8-bit eFuse OTP memory device in accordance with the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an e-fuse OTP memory device of a differential pair structure according to the present invention will be described in detail with reference to the accompanying drawings.

The e-fuse OTP memory device (hereinafter referred to as e-fuse OTP memory device) of the differential pair structure of the present invention refers to an 8-bit fuse OTP memory device designed using a TSMC 0.18 mu m process, The overall configuration of the memory device is shown in Fig.

1 is a block diagram of an eFuse memory device according to an embodiment of the present invention.

As shown in FIG. 1, the fuse OTP memory device 100 includes a control logic unit 110 for supplying an internal control signal suitable for an operation mode according to a control signal. Here, the operation mode may be classified into a read mode, a program mode, a program verification read mode, and a reset mode. The control signal is divided into a read (RD) signal, a program (PGM: Program) signal, a program verify-read enable signal (PVR_EN), and a reset (RST) signal. The operation mode and the control signal correspond to each other. Meanwhile, the PVR_EN signal distinguishes between a program-verify-read mode and a read mode. In the program verify read mode, a sensing margin test using a variable pull-up load is performed in consideration of a resistance variation of a programmed eFuse, and an operation of comparing programmed data and data stored in an eFuse memory cell do. Read mode refers to the normal lead mode that leads the program.

The fuse OTP memory device 100 includes a program column selection unit (PGM_COL_SEL) 120 for decoding an address signal ADD [2: 0] to select a program column, And a program data latch unit (PD latch) 130 for storing data programmed in a memory cell selected by the program data latch unit (PD latch). The program data latch unit 130 serves to latch the program input data DIN used to program the eFuse memory device 100 in the program mode.

Also, the fuse OTP memory device 100 is provided with an OTP cell array (hereinafter, also referred to as a "cell array") 140 for performing an operation of programming the eFUSE or reading the programmed data according to the operation mode. In the embodiment, the cell array 140 is composed of 1 row x 8 columns, and the differential pair having a small sensing resistance of the fuse link uses a differential paired eFuse OTP cell (hereinafter also referred to as a memory cell) Respectively. And the link used for this fuse (ie, the fuse link) uses 'n-poly silicon' or 'Co-silicide'. The memory cell constituting such a cell array 140 will be described in detail below with reference to Fig.

The fuse OTP memory device 100 further includes a data output buffer unit 160 receiving data from the cell array 140 according to a control operation of the control logic unit 110. The data output buffer unit 160 outputs the data through the output port ([7: 0]) (DOUT / DOUTb) or is used for the program verification read mode.

Also, the fuse OTP memory device 100 is provided with a comparator 170. The comparing unit 170 compares the program data PD [7: 0] of the program data latch unit 130 with the read data DOUT [7: 0] stored in the data output buffer unit 160 It plays a role. As a result of the comparison, the comparator 170 selectively outputs a '1' or '0' signal through a PFb (pass fail bar) pin. The signal '1' is a signal that is output when all of the 8-bits match and is normally programmed, and the signal '0' is a signal that is output when the at least one bit of the 8- This process is performed in the program verification read mode.

Next, the characteristics of the eFuse OTP memory device 100 will be described.

The fuse OTP memory device 100 uses a 1-bit program bit and an 8-bit read bit. The program time for programming the data in the memory cell 141 (FIG. 2) is 200 μs. The power supply voltage VDD used is a single power supply. The VDD voltage is used in program mode to supply sufficient program power to the eFuse link, and 3.0 to 3.6V in read mode. In addition, the number of masks in the manufacturing process was reduced by using only 3.3V MOS transistors.

Main features of the eFuse memory device 100 described above are shown in Table 1 below.

Item Key Features Manufacture process TSMC 0.18μm process OTP cell array size 1 row * 8 columns Fuse Type n-poly silicon (Co-silicide) Supply voltage 3.0V to 3.6V Temperature -40 ° C to 125 ° C
Operation mode Program mode Program verification read mode
(Program-Verify-Read mode) Normal Read mode Reset mode Program bit / Read bit 1bit / 8bit Program voltage 3.9V Program time 200 μs Access time 200 ㎱

Next, the configuration of the memory cell 141 applied to the eFuse OTP memory device 100 will be described with reference to FIG. FIG. 2 is a circuit diagram showing a fuse cell in which a differential pair, which is a unit memory cell constituting the cell array 140 of FIG. 1, is shown.

As shown in FIG. 2, the memory cell 141 is composed of a total of four MOS transistors and two eFuse elements and is symmetrical to each other.

Specifically, the memory cell 141 is divided into a first data storage unit 142 for storing program data and a second data storage unit 144 for storing complementary program data.

The first data storage unit 142 is configured such that the first NMOS MN1 and the second NMOS MN2 are connected in series and the first eFuse 1 is connected to the node N1 to which the first NMOS MN1 and the second NMOS MN2 are connected. The first NMOS MN1 receives a 'PGM_BL_SEL' signal for selecting a bit line BL through a gate terminal thereof, and a ground voltage Vss line is connected to a source terminal thereof. A read word line (RWL) is connected to the gate terminal of the second NMOS (MN2), and a bit line (BL) is connected to the drain terminal.

The second data storage unit 144 includes the same elements as the first data storage unit 142 and is configured to be symmetrical with respect to each other. That is, the third NMOS MN3 and the fourth NMOS MN4 are serially connected. And a second eFuse 2 is connected to the node N2 to be connected. The third NMOS transistor MN3 receives a 'PGM_BLb_SEL' signal for selecting a program bit line BLb through a gate terminal thereof, and a ground voltage Vss line is connected to a source terminal thereof. A read word line (RWL) is connected to the gate terminal of the fourth NMOS (MN4), and a bit line (BLb) is connected to the drain terminal.

The first NMOS transistor MN1 and the third NMOS transistor MN3 are used as program transistors capable of flowing a large program current and the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are used as a program transistor It is used as a read-only transistor that can be reduced.

A selection line SL is connected to a node N3 to which the first eFuse 1 and the second eFuse 2 are connected. In the program mode, a program voltage of 3.9 V is applied to flow an overcurrent to the fuse link, and a read mode, a program verify read mode And 0 V in the reset mode.

Meanwhile, the first to fourth NMOSs MN1, MN2, MN3, and MN4 of the memory cell 141 have different states according to the program data of '0' or '1'.

That is, the case where the program data is '1' will be described first. At this time, the PGM_BL_SEL signal and the PGM_BLb_SEL signal are applied at 3.9 V and 0 V, respectively. Accordingly, the first eFuse 1 becomes a blowing state due to the overcurrent flowing through the first eFuse 1 and the first NMOS MN1. Since the third NMOS MN3 is in the off state, the second NMOS transistor MN2 is turned off. Therefore, the second NMOS transistor MN3 is turned off, The eFuse 2 is not blown.

On the other hand, the program data is '0'. In this case, on the contrary, the first NMOS MN1 has an off state and the third NMOS MN2 has an on state. Therefore, only the second eFuse 2 is in a blowing state, and the first eFuse 1 is not blown.

And the memory cell 141 provides different cell bias conditions in the program mode and the read mode. The cell bias voltage according to the program mode and the read mode is shown in [Table 2].

Program mode Reading mode Unselected Cell Selected Cell DIN 0 One 0 One 0 One RWL 0 0 0 0 VDD 7VDD PGM_BL_SEL 0V 0V 0V VDD 0V 0V PGM_BLb_SEL 0V 0V VDD 0V 0V 0V SL VDD VDD VDD VDD 0V 0V BL Floating Floating Floating Floating 0V VDD BLb Floating Floating Floating Floating VDD 0V

3 is a circuit diagram of a 1-row by 8-column cell array constituting the cell array of FIG.

It can be seen that the memory cells shown in FIG. 2 are arranged in one row by eight columns. Of course, only two memory cells are illustrated with a portion of the memory cell omitted.

In the cell array, the read word line RWL and the select line SL are in the row direction, and BL [7: 0], BLb [7: 0], PGM_BL_SEL [7: 0] and PGM_BLb_SEL [7: 0] ] Are routed in the column direction.

The operation timing of the fuse OTP memory device 100 will now be described.

Figures 4A and 4B show timing diagrams in which the eFuse OTP memory device of Figure 1 operates in a program mode and a read mode.

4A, when the address signal A [2: 0] and the input data DIN are applied (at time points a and b), the program signal is activated from the point c to the high state. Then, the control logic unit 110 programs one bit of the input data into the memory cell selected by the program column selecting unit 120.

The program is run during the program time t _PGM . When the program is completed, the address signal A [2: 0] and the input data DIN become low.

4B is a timing diagram in the read mode. In the read mode, when the read signal RD is activated to a high state (a time point), the control logic unit 110 outputs 8-bit data stored in eight memory cells constituting the cell array 140 to the access time parameter t _And outputs it through the data output buffer unit 160 at time point b after _AC time.

On the other hand, the fuse OTP memory device 100 must have the sensing capability of the eFuse link programmed in the program verify read mode and the read mode. That is, since the e-fuse OTP memory device 100 reduces the resistance of the e-fuse link programmed during the data retention time, it is necessary to prevent the sensing failure from occurring even in this case. To this end, the present invention provides a sensing margin test function using a variable pull-up load. See FIG.

FIG. 5 is a diagram illustrating a configuration of a variable pull-up load circuit for performing a sensing margin test in consideration of fluctuations of an eFuse resistance programmed in the cell array shown in FIG.

As shown in FIG. 5, the variable pull-up load circuit 150 includes first and second pull-up load transistors MP1 and MP2 for a read mode, which are PMOS devices and are supplied with a BL_LOADb signal, And a third and a fourth pull-up load transistor (MP3) MP4 for program verify reading which are constituted by elements and are supplied with a TM_BL_LOADb signal. The first and third pull-up load transistors MP1 and MP3 are connected to the bit line BL and the second and fourth pull-up load transistors MP2 and MP4 are connected to the bit line BLb and the second pull- . The first through fourth pull-up transistors MP1, MP2, MP3, and MP4 are all designed to maintain a high-impedance state.

Also, the variable pull-up load circuit 150 includes first and second NMOS transistors MN1 and MN2 receiving a BL_PCG signal for BL pre-charge.

The first transistor MN1 is connected to the first and third pull-up load transistors MP1 and MP3 and the second transistor MN2 is connected to the second and fourth pull-up load transistors MP2 and MP4 ).

The variable full-up load circuit 150 having such a configuration is configured such that when the read word line (RWL) signal of the memory cell 141 is activated to the power supply voltage (VDD), the BL_LOADb signal is applied to the first and second pull- The bit lines BL and BLb are pulled up to the power supply voltage VDD by the transistors MP1 and MP2. At this time, the third and fourth pull-up load transistors (MP3) MP4 are turned off.

Since the impedances of the first through fourth pull-up transistors MP1, MP2, MP3 and MP4 are large, the bit line BL connected to the un-programmed eFUSE maintains the ground voltage VSS, On the other hand, the bit line BL connected to the programmed eFuse is pulled up to the power supply voltage VDD. If the un-programmed memory cell 141 is read, the power supply voltage VDD, which is the precharge voltage of the bit line BL, is applied to the second NMOS MN2 and the fourth NMOS MN4 shown in FIG. And is discharged to the ground (GND) through the fuse (eFuse 1) and the second eFuse (eFuse 2).

On the other hand, the third and fourth pull-up load transistors MP3 (MP4) are used only during the test of the OTP IP, in which the first and second pull-up load transistors MP1 and MP2 are off.

Therefore, the third and fourth pull-up load transistors MP3 (MP4) are larger than the impedances of the first and second pull-up load transistors MP1 and MP2. For this reason, the differential voltage in the program verify read mode is less than the differential voltage in the read mode, and the eFuse resistance that can be sensed must be greater than the read mode.

As a result, a difference value of the fuse resistance that can be sensed is generated, and this resistance difference value becomes a margin resistance during the data retention time. The margin test for the resistance variation of the eFuse link programmed through the margin resistor can be performed.

Next, a circuit for sensing and outputting a differential voltage between the bit lines BL and BLb will be described with reference to FIGS. 6A and 6B.

6, when the voltage of the bit line BL (BLb) is pulled up by the variable pull-up load circuit shown in FIG. 5, the BL sense amplifier detects differential voltage between the bit lines BL and BLb A circuit diagram of an amplifier (BL S / A, BL Sense Amplifier) is shown.

BL S / A 161 is a S / A-based D flip-flop circuit that senses the differential voltage between BL and BLb and uses a negative edge triggered D F / F. An SR latch circuit is also provided to latch the sensed differential voltage.

During the high period of SAENb, the BS S / A 161 maintains the ground voltage VSS at nodes N1 and N2. The SR latch circuit latches the data in the previous state. Then, when the SAENb is in the low state, it senses a differential voltage between the bit lines BL and BLb and outputs the differential voltage through the data output ports DOUT and DOUTb.

At this time, FIG. 6A resets DOUT to '0' in the reset mode, and FIG. 6B resets DOUT to '1' in the reset mode.

The BL sense amplifier 161 performs the function of the data output buffer unit 160. That is, the data output buffer 160 performs all or some of the functions of the BL sense amplifier 161.

The present invention also provides a function of checking whether or not data is normally programmed in a memory cell of the fuse OTP memory device 100. This will be described with reference to FIGS. 7 and 8. FIG.

FIG. 7 is a circuit diagram of the comparison unit shown in FIG. 1, and FIG. 8 is a timing diagram when the eFuse memory device according to the embodiment of the present invention operates in the program verification read mode.

The operation of the comparator 170 using the dynamic pseudo NMOS (NMOS) logic circuit is as follows.

After the program mode, the program verify read mode is performed when the enable signal COMP_EN for data comparison is activated to a high state.

The read signal and the PVR_EN signal are all in a high state in accordance with the program verify read mode and during a predetermined access time t _AC the comparator 170 compares the program data latched in the program data latch unit 130 [7: 0]) stored in the data output buffer unit 160 and the read data DOUT [7: 0] stored in the data output buffer unit 160 coincide with each other.

Then, the comparison result is output through the PFb pin after the access time (t _AC ) has elapsed. When the program data PD [7: 0] and the read data DOUT [7: 0] match, the match signal maintains the power supply voltage VDD, (VDD). On the other hand, if at least one bit of the program data PD [23: 0] and the read data DOUT [23: 0] is different, the match signal is discharged to 0V and PFb outputs 0V.

Therefore, the fuse OTP memory device 100 can test whether data is normally programmed in the memory cell 141 even in a packaged state.

On the other hand, a power IC chip provided with the e-fuse OTP memory device 100 may generate a glitch pulse unnecessary for a read signal due to power or ground noise due to a large switching current, The fact that the circuit can not be trimmed normally has been described above.

Therefore, the present invention provides an e-fuse OTP memory device having a high noise immunity that can keep the program data read in the read mode. To this end, the e-fuse OTP memory device 100 is provided with an IRD (Internal Read Data) control circuit 180.

IRD control circuit 180 refers to Fig.

9, the IRD control circuit 180 includes a first inverter receiving a read signal, a second NAND receiving an output of the first inverter and an output of the first NAND, an output of the second NAND, A third NAND receiving the IRSTb signal, and a fourth NAND receiving the read signal inverted through the third NAND and the second inverter and outputting the IRD signal. At this time, the first NAND receives the IRSTb signal and the output of the second NAND, performs a logic operation, and applies the output to the input signal of the second NAND.

The IRD control circuit 180 configured as described above prevents the re-read mode from entering the read mode until power is turned off even if a glitch pulse occurs in the read signal. That is, the IRD signal maintains the high state even when the read signal goes from the high state to the low state, thereby preventing the re-reading mode from being performed.

On the other hand, the present invention prevents forcible blowing of the fuse link by EM (Electro-Migration) phenomenon, thereby improving reliability.

This will be described with reference to FIG. 10, which illustrates a control timing diagram of the fuse OTP memory device 100. FIG.

Referring to FIG. 10, when the read signal is in the high state, the IRD signal also switches to the high state and enters the read mode. Then, the data of the memory cell 141 is transferred to the BL and BLb by the RWL signal and the differential input is sensed by the SAENb signal of the BL sense amplifier 161.

The sensing operation for the bit line BL is completed using a method of applying a pulse to the word line WL (i.e., a pulsed WL driving method) And the fourth NMOS MN2 (MN4) are turned off.

Since the DC current flowing through the second and fourth NMOSs MN2 and MN4 is interrupted, the reliability of the e-fuse OTP memory device 100 can be secured.

By doing so, it is possible to prevent the problem that the fuse link is unintentionally disconnected due to the conventional EM (Electro-Migration) phenomenon. That is, when the read word line (RWL) signal is kept in a high state in the past, the second and fourth NMOSs MN2 and MN4 shown in FIG. 2 and the first and third pull- Since the up-load transistor (MP1) (MP3) is always on, the DC link of several tens of microamperes continues to flow through the fuse link and the e-fuse link is undesirably broken, If it is broken, it is an error that the information to be read as 'Low' is read as 'High'. At this time, the fuse link is programmed to be in the disconnected state as 'High', and the state not to be disconnected as 'Low'.

Meanwhile, the present invention may cause a change in electrical characteristics in a state where the power IC chip is packaged. Thus, the power IC chip also provides the ability to program data into the memory cell even in the packaging state.

The data program uses VDD, which is a single power source, and is performed in the program mode. That is, when the program mode is performed, the program data is supplied to the gate terminals of the first and third NMOSs MN1 and MN3 of FIG. 2 and the program voltage (i.e., 3.9v) is supplied through the selection line SL, do. Of course, when the mode is not a program mode but a read mode, the switching voltage of the selection line SL will maintain 0V.

When the program voltage is supplied in this way, the fuse link is blown, and as a result, it becomes possible to reprogram the data to the fuse link.

Here, there is a need to reduce the voltage drop caused by the switching current between the power supply voltage (VDD) and the ground voltage (VSS) when the program mode is performed. Thus, the SL switching circuit shown in Fig. 11 can be used.

Referring to the configuration of the SL switching circuit 190 shown in FIG. 11, a PMOS and an NMOS are connected in series between a power supply voltage VDD and a ground power supply VSS. And the node between the PMOS and the NMOS is connected to the select line SL.

The first NAND and the first to sixth inverters are connected in series to the gate of the PMOS, and the second NAND and the 1-1 to 5-1 inverters are serially connected to the gate of the NMOS. Here, the first NAND receives the first signal and the output signal of the fourth inverter, and the second NAND receives the second signal and the output signal of the fourth inverter as inputs. The second signal is the signal through which the first signal is output via the inverter.

By doing so, the voltage drop occurring between the power supply voltage VDD and the ground voltage VSS can be reduced.

Next, an experimental result of the sensing resistance of the eFuse link programmed in the eFuse OTP memory device of the present embodiment will be described.

The fuse OTP memory device 100 of the present invention used in the experiment was designed with 8 bits using the TSMC 0.18 mu m process. The simulation conditions are the power supply voltage (VDD) = 3.6V and the FF model parameter, -40 ° C.

The experimental results are shown in Tables 3 and 4 below. Table 3 shows the experimental results of the sensing resistance of the eFuse link programmed in the read mode. Table 4 shows the experimental results of the sensing resistance of the eFuse link programmed in the program verify reading mode.

VDD Temp SS model SF model TT model FS model FF model
3.0v
-40 ° C 4K 3K 4K 4K 3K 25 ℃ 5K 4K 4K 4K 4K 125 ℃ 5K 4K 5K 5K 4K
3.3v
-40 ° C 3K 3K 3K 3K 3K 25 ℃ 4K 3K 3K 4K 3K 125 ℃ 4K 4K 4K 4K 4K
3.6v
-40 ° C 3K 3K 3K 3K 2K 25 ℃ 3K 3K 3K 3K 3K 125 ℃ 4K 3K 3K 4K 3K

VDD Temp SS model SF model TT model FS model FF model
3.0v
-40 ° C 30K 24K 26K 29K 22K 25 ℃ 35K 28K 30K 33K 26K 125 ℃ 43K 34K 37K 40K 31K
3.3v
-40 ° C 25K 20K 21K 23K 19K 25 ℃ 29K 23K 25K 27K 22K 125 ℃ 35K 27K 29K 32K 25K
3.6v
-40 ° C 20K 16K 17K 18K 15K 25 ℃ 23K 18K 20K 22K 17K 125 ℃ 29K 23K 24K 26K 21K

In this case, the sensing resistance of the read mode is 2 k ?, and the sensing resistance of the program verify reading mode is 15 k ?. As a result, it can be confirmed that the eFuse memory device 100 of the present invention can normally sense the programmed eFuse resistance as long as it does not drop below 13 k ?.

FIG. 12 shows experimental results of the program verification read mode according to the embodiment of the present invention. FIG. 12A shows a case where the program is programmed with '1' and FIG. 12B shows a case where the program is programmed with '0'.

In this case, when the read signal is activated, output data is output after a predetermined access time.

Then, when the enable signal for comparison is activated, the PFb of the comparator 170 compares the program data PD [7: 0] with the read data DOUT [7: 0] and outputs the result . As a result of comparison, if the program data PD [7: 0] and read data DOUT [7: 0] coincide, 'PASS' is outputted. Otherwise, 'FAIL' is output.

13 is an image diagram showing the layout of an 8-bit eFuse OTP memory device in accordance with the present invention.

The layout area is 189.625 占 퐉 占 138.850 占 퐉 and 0.0263 mm2.

As described above, the present invention provides a fuse OTP memory device that is robust against noise such as a glitch pulse and prevents the fuse link from forcibly blowing due to EM phenomenon. .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent that modifications, variations and equivalents of other embodiments are possible. Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: E-fuse OTP memory device 110: Control logic part
120: program column selection unit 130: program data latch unit
140: OTP cell array 141: memory cell
150: variable pull-up load circuit 160: data output buffer unit
161: BL sense amplifier 170:
180: IRD control circuit 190: SL switching circuit

Claims (9)

A cell array comprised of one or more OTP memory cells; And
A differential pair structure including an IRD control circuit for performing a read mode when a glitch pulse is generated in the read signal when the program data provided to the OTP memory cell is output in accordance with a read signal in a read mode, This fuse is an OTP memory device. The method according to claim 1,
The IRD control circuit includes:
And outputs an IRD signal so that the current read mode is continuously performed when the read signal is in a high state. 3. The method of claim 2,
Fuse OTP memory device having a differential pair structure in which the IRD signal maintains a high state even when the read signal goes to a low state, so that data output by the read signal remains intact. 3. The method of claim 2,
Wherein the read mode is performed when the IRD signal goes high from a low state and the read mode is continuously performed until a power of the IC chip is down. The method according to claim 1,
The IRD control circuit includes:
A first inverter receiving a read (RD) signal;
A second NAND receiving an output of the first inverter and an output of the first NAND;
A third NAND receiving an output of the second NAND and an IRSTb signal;
And a fourth NAND for receiving an output of the third NAND and a read (RD) signal inverted through the second inverter and outputting an IRD signal,
Wherein the first NAND gate is configured to receive the IRSTb signal and the output of the second NAND gate and to apply a logically computed signal to the input signal of the second NAND gate. The method according to claim 1,
A first NMOS and a second NMOS connected in series;
A first eFuse connected to the connection node of the first NMOS and the second NMOS;
A third NMOS and a fourth NMOS connected in series;
A second eFuse connected to the connection node of the third NMOS and the fourth NMOS;
A read word line (RWL) coupled to the gates of the second NMOS and the fourth NMOS; And
Further comprising a sense amplifier sensing a differential voltage between the bit line BL and the bit line BLb when the voltage of the bit line BL (BLb) is pulled up by the variable pull-up load circuit,
And the second NMOS and the fourth NMOS are turned off when the sensing operation for the bit line BL is completed. The method according to claim 6,
Fuse OTP memory device having a differential pair structure in which a DC current is shut off when the second NMOS and the fourth NMOS are turned off. 8. The method of claim 7,
Fuse OTP memory device of the differential pair structure in which the driving method of applying the pulse to the word line (WL) is used. The method according to claim 6,
The variable pull-up load circuit performs a sensing margin test, and the variable pull-up load circuit includes a differential pair structure in which a impedance of a full-up load of a bit line pre-charge circuit used in a program verify read mode and a read mode is varied, Fuse OTP memory device.

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